Reuse-Based Test Planning for Core-Based Systems-on-Chip - Cota, Érika; Lubaszewski, Marcelo (Anais do Concurso de Teses e Dissertações da SBC (CTD-SBC), 2004)
This work proposes two test planning heuristics that aim at reducing both the test costs of a core-based system and the computational effort to devise a cost-effective test plan. The proposed approaches target systems with distinct connection models, and the test planning algorithms are modeled accordingly. For systems connected through dedicated wires and buses, the test planning is modeled as a multi-variable optimization problem,and a search heuristic is implemented. For systems connected through a network-on-chip, the test planning is modeled and solved as a resource-constrained scheduling. Experimental results are presented for both techniques, and clearly show the variety of trade-offs that can be explored using the proposed reuse-based models, and the effectiveness of such methods on defining a cost-effective system test plan.