Enzo Ibiapina, Benjamin Silva, and Ivan Silva. 2024.
 Implementation of 32-bit Multiplication Unit for a Out-of-Order RISC-V Processor utilizing Radix-4 Booth Algorithm and Wallace Tree. In <em>Anais da XII Escola Regional de Computação do Ceará, Maranhão e Piauí</em>, setembro 11, 2024, Parnaíba/PI, Brasil. SBC, Porto Alegre, Brasil, 291-296. DOI: <a href="https://doi.org/10.5753/ercemapi.2024.243779">https://doi.org/10.5753/ercemapi.2024.243779</a>.