Correction of Adjacent Errors with Low Redundant Matrix Error Correction Codes - Gracia-Moran, Joaquin; Saiz-Adalid, Luis-J.; Baraza-Calvo, Juan-Carlos; Gil, Pedro (Anais do Latin-American Symposium on Dependable Computing (LADC); 2018: Anais do VIII Latin-American Symposium on Dependable Computing, 2018)
The continuous growth of the integration scale in CMOS circuits has derived in an increase in the memory systems capacity, but also in their fault rate. In this way, the probabilities of suffering Single Cell Upsets (SCUs) or Multiple Cell Upsets (MCUs) has thus raised. Traditionally, Error Correction Codes (ECCs) are used in memory systems to correct errors. However, when using ECCs, it is necessary to find a good balance between the redundancy of the code; the area, power consumption and delay overheads of the encoding and decoding circuits; and the error coverage achieved. In this work, we present two new low-redundant matrix ECCs that are able to correct different types of adjacent errors. Both codes have the same error coverage, but different levels of redundancy. In this way, we have been able to study the influence of these different levels of low redundancy in the area, power consumption and delay overheads. We have also compared our proposals to a well-known matrix code, in terms of overhead vs. coverage using a recently introduced metric. In all cases, our proposals get better scores.