Investigating the Relative Performance of Static and Dynamic Instruction Scheduling - Tate, Daniel; Steven, Gordon; Findlay, Paul (Anais do International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD); 1999: Anais do XI Symposium on Computer Architecture and High Performance Computing, 1999)
There are two distinct groups of research into ILP. Those that strongly favour static instruction scheduling and those that favour dynamic instruction scheduling. This paper introduces powerful static and dynamic scheduling models and combines them within the framework of a single simulation environment. Both individual models achieve respectable speedups; dynamic schedullng significantly out-performs static scheduling when an idealised processor model with perfect branch prediction is used. However, when a realistic branch predictor is substituted, the roles are reversed, and static scheduling achieves the higher performance. Similarly, static scheduling performs better in the absence of branch prediction or when processor resources are restricted. Finally, we combine static scheduling with out-of-order instruction issue. Disappointingly, when an ideal out-of-order processor is used, scheduled code fails to match the performance of unscheduled code. Furthermore, with realistic branch predictlon, out-of-order issue fails to improve the performance of scheduled code.