A Proposal for a Parallel Programming Support for Multi-LAN platforms - Arantes, Luciana; Folliot, Bertil; Sato, Liria M.; Sens, Pierre (Anais do International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD); 1999: Anais do XI Symposium on Computer Architecture and High Performance Computing, 1999)
In the first part of this article, we present our proposal for a distributed shared memory system (DSM) for an interconnection of local-area networks (LANs). Our multi-LAN DSM will be composed of a set of per LAN lazy release consistency (LRC) memory model DSM systems. For controlling shared-memory updates, the LRC protocol of cach DSM will use the barrier-lock logical clocks, instead of the traditional per processor vector ones. This replacement provides modularity and scalability to some extent. The other enhancements to be added to the protocol aim the reduction of the number of messages and the volume of data exchanged between LANs for the sake of applications' performance. Data pre-fetching, simulation of a LAN-level cache and hierarchical execution of barriers are some of the strategies to be adopted. In the second part of the paper, we discuss the advantages of using the CPAR language for the development of parallel applications which run on top of shared-memory hierarchical platforms such as multi-LAN DSMs.