Volume Rendering FPGA Hardware - Hesser, J.; Kugel, A.; Singpiel, H.; Vettermann, B.; Männer, R. (Anais do International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD); 1999: Anais do XI Symposium on Computer Architecture and High Performance Computing, 1999)
This paper discusses the implementation of volume rendering on FPGA hardware. The FPGA board is based on a 2x2 matrix of FPGA devices that are reprogrammed for different data processing tasks that occur during rendering. Moreover, it is shown how branch and data hazards are overcome in the pipelined system by multithreading.