The Performance of Cache Coherency in SCI-based Multiprocessors - Hexsel, Roberto A.; Topham, Nigel P. (Anais do International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), 1996)
The Scalable Coherent Interface (SCI) is an IEEE/ANSI standard that defines a hardware platform for scalable shared-memory multiprocessors. This paper contains a quantitative performance evaluation of SCI-connected multiprocessors that assesses both the communication and cache coherence subsystems. 1D, 2D and 3D tori with 16 and 64 nodes are investigated. For the architecture (100MHz Sparc, 2 levels of caches) and workload simulated, it was found that raw network bandwidth seen by a processing element is under 100Mbytes/s. The 3-D toros is 10-15% faster than the 2-D toros for programs that generate high leveis of network traffic. Otherwise, the differences in performance between 2-D and 3-D tori are negligible.