Extending DLXsim for Parallel Architectures - Mendes, Celso L. (Anais do International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD); 1994: Anais do VI Simpósio Brasileiro de Arquitetura de Computadores e Processamento de Alto Desempenho, 1994)
This paper presents two extensions of a RISC processor called DLX. We extend DLX's functionality for a vector and for a parallel architecture. The vector extension, DLXV, has pipelined vector functional units and is able to perform chained vector operations. The parallel extension, DLXMP, is a message-passing multicomputer with a basic DLX on each node. We present simulators for both extensions, describe their major features, and show examples of their use.