SPECint95 Performance of an Implementation of the Dynamically Trace Scheduled VLIW Architecture - Souza, Alberto Ferreira de; Rounce, Peter (Anais do International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), 1998)
Dynamically trace scheduled VLIW (DTSVLIW) architectures can be used to implement machines that execute code of current RISC or CISC instruction set architectures in a VLIW fashion, delivering instruction level parallelism with backward code compatibility. This paper presents preliminary SPECint95 performance mesuraments of the DTSVLIW architecture, obtained with a simulator which has been implemented in C.