Exploring memory hierarchy with ArchC - Viana, P.; Barros, E.; Rigo, S.; Azevedo, R.; Araujo, G. (Anais do International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), 2003)
We present the cache configuration exploration of a programmable system, in order to find the best matching between the architecture and a given application. Here, programmable systems composed by processor and memories may be rapidly simulated making use of ArchC, an architecture description language (ADL) based on SystemC. Initially designed to model processor architectures, ArchC was extended to support a more detailed description of the memory subsystem, allowing the design space exploration of the whole programmable system. As an example, it is shown an image processing application, running on a SPARC-V8 processor-based architecture, which had its memory organization adjusted to minimize cache misses.