Optimizing packet capture on symmetric multiprocessing machines - Varenni, G.; Baldi, M.; Degioanni, L.; Risso, F. (Anais do International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD); 2003: Anais do XV Symposium on Computer Architecture and High Performance Computing, 2003)
Traffic monitoring and analysis based on general purpose systems with high speed interfaces, such as Gigabit Ethernet and 10 Gigabit Ethernet, requires carefully designed software in order to achieve the needed performance. One approach to attain such a performance relies on deploying multiple processors. This work analyses some general issues in multiprocessor systems that are particularly critical in the context of packet capture and network monitoring applications. More important, a new algorithm is proposed to coordinate multiple producers concurrently accessing a shared buffer, which is instrumental in packet capture on symmetrical multiprocessor machines.