Ultra-Fast CPU Performance Prediction: Extending the Monte Carlo Approach - Srinivasan, Ram; Cook, Jeanine; Lubeck, Olaf (Anais do International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD); 2006: Anais do XVIII International Symposium on Computer Architecture and High Performance Computing, 2006)
Performance evaluation of contemporary processors is becoming increasingly difficult due to the lack of proper frameworks. Traditionally, cycle-accurate simulators have been extensively used due to their inherent accuracy and flexibility. However, the effort involved in building them, their slow speed, and their limited ability to provide insight often imposes constraints on the extent of design exploration. In this paper, we refine our earlier Monte Carlo based CPI prediction model (Srinivasan et al., 2006) to include software assisted data-prefetching and an improved memory model. Software-based prefetching is becoming an increasingly important feature in modern processors but to the best of our knowledge, existing frameworks do not model it. Our model uses micro-architecture independent application characteristics to predict CPI with an average error of less than 10% when validated against the Itanium-2 processor. Besides accurate performance prediction, we illustrate the applications of the model to processor bottleneck analysis, workload characterization and design space exploration