High Level Power and Energy Exploration Using ArchC - Gupta, T.; Bertolini, C.; Heron, O.; Ventroux, N.; Zimmer, T.; Marc, F. (Anais do International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD); 2010: Anais do XXII International Symposium on Computer Architecture and High Performance Computing, 2010)
With the increase in the design complexity of MPSoC architectures, estimating power consumption is very complex and time consuming at lower level of abstraction. We propose a methodology using ArchC named Power-ArchC for a fast high-level estimation of processor power consumption. Power values are obtained by an instruction level power characterization at gate level. The requirements for power evaluation infrastructure are compatible processor models written in ArchC and RTL, and the Technology library. We show power results for a 32-bit MIPS processor with different benchmarks, based on 45nm technology.