Wang, Z., 		Jiménez, D., 		Zhang, T., 		Loh, G., & 		Xie, Y.
(2016).
 Building a Low Latency, Highly Associative DRAM Cache with the Buffered Way Predictor.
In <em>Anais do XXVIII International Symposium on Computer Architecture and High Performance Computing</em>, (pp. 109-117). Porto Alegre: SBC.