Trimming the ISA to Optimize Area and EDP in Heterogeneous CMPs - Souza, Jeckson Dellagostin; Beck, Antonio Carlos Schneider (Anais do International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD); 2019: Anais do XXXI International Symposium on Computer Architecture and High Performance Computing, 2019)
Asymmetric multicores of single-ISA are great solutions for efficient processor resource usage. These processors can maintain software productivity with high energy efficiency by smartly migrating tasks to low-energy cores when high performance is not necessary. This work proposes going one step further by exploiting that 1) the pipelines of specialized instructions (e.g., SIMD - Single Instruction Multiple Data and FP - Floating Point) have extremely high cost (in some cases responsible for more than half of the core area); and 2) these instructions are not used as often as the instructions from the base ISA. By trimming the ISA of some cores in a processor, it is possible to create a Partially Heterogeneous ISA (PHISA) system. PHISA is composed of heterogeneous cores that share the base ISA, but are asymmetric in functionality (only some of these cores implement the full ISA with specialized instructions). PHISA uses transparent migrations of tasks to maintain support for the extended instructions while freeing valuable area and power from the processor design. In this work, we show how PHISA can be used to improve the performance by up to 32% and reduce energy consumption by up to 82% when compared to reference processors in embedded scenarios.