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 Memory Latency: to Tolerate or to Reduce?. In <em>Anais do XII Symposium on Computer Architecture and High Performance Computing</em>, outubro 24, 2000, São Pedro/SP, Brasil. SBC, Porto Alegre, Brasil, 15-22. DOI: <a href="https://doi.org/10.5753/sbac-pad.2000.41199">https://doi.org/10.5753/sbac-pad.2000.41199</a>.