A Java-to-ARM Hardware Code Translator - Hsu, Ta-Yung; Ton, Lee-Ren; Chang, Lung-Chung; Chung, Chung-Ping (Anais do International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD); 2000: Anais do XII Symposium on Computer Architecture and High Performance ComputingDO - 10.5753/sbac-pad.2000.41202, 2000)
Java is one of the most popular programming languages. Various methods to run Java instructions (called Java bytecodes) have been developed, but each has its drawback. Therefore, we propose the concept of a Java/ARM dual-mode processor, which offers a better alternation to run Java and is still compatible with ARM for existing C applications. When executing the Java applets/applications, the bytecode instructions can be executed by the dual-mode processor on-the-fly. This is achieved by the proposed Java-to-Arm hardware code translator which is built in between the instruction fetcher and the instruction decoder. In the Java execution mode, the translator converts each bytecode into one or more ARM instructions on-the-fly. Besides, an ARM instructions folding technique is proposed to enhance the performance by combining the translated but not decode ARM instructions. Simulation results show that up to 15% performance gain can be achieved comparing to the original translator without folding.