Analyzing Branch Prediction Impact on the Effectiveness of Instruction Prefetch - Santos, Tatiana G. S. dos; Pilla, Maurício L.; Dal Pizzol, Guilherme; Bampi, Sergio; Navaux, Philippe O. A. (Anais do International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD); 2000: Anais do XII Symposium on Computer Architecture and High Performance ComputingDO - 10.5753/sbac-pad.2000.41215, 2000)
In order to provide a high instruction throughput for advanced superscalar models, L1 caches must achieve a low miss rate with no increase orminimum change in L1 capability. Prefetch mechanism anticipate data from memory to L1 caches ahead of its request by the CPU instruction executing flow. These kind of schemes reduce the miss occurence as well as help to hide the memory access latency. The wrong path prefetch anticipates the next block and also the taken target of a branch. This work analyzes how the branch prediction may influence in the performance of this prefetch scheme. The number of wasted cycles and the effects of cache pollution and prefetch overlap are also presented.