Exploiting Reuse with Dynamic Trace Memoization: Evaluating Architectural Issues - Costa, Amarildo T. da; França, Felipe M. G.; C. Filho, Eliseu M. (Anais do International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), 2000)
Employing memoization tables to skip the execution of dynamic sequences of redundant instructions, our Dynamic Trace Memoization (DTM) mechanism extends the concept of instruction reuse to larger grain units. This work evaluates three critical architectural issues concerning the feasability of DTM: (i) The cost-efectiveness of trace level reuse – the paper shows that a balance between the sizes of the single instruction memoization table and the trace memoization table produces higher speedups and does not need a higher number of read ports in the trace memo table; (ii) Register file pressure – for the SPECInt95 and APECFp95 benchmark suites, DTM requires no extra read ports; (iii) Floating-point apparatus – in contrast with the speedup of 8.4% obtained by the SPECInt95, the SPECFp95 presented a speedup of 7% considering a DTM mechanism which ignores the floating-point operations.