Gonçalves, R., Ayguadé, E., Valero, M., & Navaux, P. (2000). A Simulator for SMT Architectures: Evaluating Instruction Cache Topologies. In Anais do XII Symposium on Computer Architecture and High Performance Computing, (pp. 279-286). Porto Alegre: SBC. doi:10.5753/sbac-pad.2000.41226