R. Gonçalves, E. Ayguadé, M. Valero, and P. Navaux. " A Simulator for SMT Architectures: Evaluating Instruction Cache Topologies", in Anais do XII Symposium on Computer Architecture and High Performance Computing, São Pedro/SP, 2000, pp. 279-286, doi: https://doi.org/10.5753/sbac-pad.2000.41226.