Gonçalves, Ronaldo, 		Ayguadé, Eduard, 		Valero, Mateo, E 		Navaux, Philippe.
" A Simulator for SMT Architectures: Evaluating Instruction Cache Topologies" <em>Anais do International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD)</em> [Online], (24 outubro 2000)