A Simulator for SMP Platforms based on Multithreading Processors - Martins, F. R. S.; Aude, J. S. (Anais do International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD); 2000: Anais do XII Symposium on Computer Architecture and High Performance ComputingDO - 10.5753/sbac-pad.2000.41228, 2000)
This work describes the design, implementation and use of a simulator for SMP platforms based on multithreading processors. It has been conceived as a simulator for the Multiplus multiprocessor SMP processing element, which will be based on the use of NCESPARC+ processors. The simulator can run applications from the Splash benchmark, which is often used in the evaluation of shared memory parallel systems. Due to some results produced by the simulator, modifications have been introduced in the original definition of the NCESPARC+ architecture. These modifications and some other architectural changes to increase the throughput of the Processing Element memory system are discussed in this paper. In addition, simulation results for three applications are also presented.