Hardware Implementation of Multicast Communication for Interconnection Networls - Cota, I. N.; Aude, J. S. (Anais do International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD); 2000: Anais do XII Symposium on Computer Architecture and High Performance Computing, 2000)
This work is concerned with the implementation of hardware resources to support multicast communication on the Multiplus distributed shared memory multiprocessor. The multicast messages to be transmitted are those required for an efficient implementation of directory-based cache coherence protocols. To achieve this goal, a redesign of the current implementation of the Multiplus multistage interconnection network is proposed. This paper presents the main concepts of the overall redesign and describes the message transmission modes, the cache coherence protocols, the network switching element control logic and the overall multistage interconnection network architecture which have been conceived. An implementation of the network switching element on an Altera EPLD has been carried out from a VHDL description of the circuit functionality.