CLC-A: An Adaptive Implementation of the Column Line Code (CLC) ECC - Silva, Felipe; Muniz, Adahil; Silveira, Jarbas; Marcon, César (Symposium on Integrated Circuits and Systems Design (SBCCI); 2020: Anais do XXXIII Symposium on Integrated Circuits and Systems Design, 2020)
Column-Line-Code (CLC) is an Error Correction Code (ECC) designed to correct multiple errors in memory devices for critical applications. CLC has originally two decoder modes: CLC Standard (CLC-S) and CLC Extended (CLC-E). CLC-E presents higher efficacy in correcting multiple errors, although consuming more area, dissipating more power, and presenting higher delay than CLC-S, which impacts the overall system performance. This paper proposes the CLC Adaptive (CLC-A), an alternative CLC mode that introduces a Syndrome Analyzer circuit, allowing the system to decide if a second error checking is required to correct the data. The experimental results show that CLC-A reaches higher error correction rates than CLC-S and similar values of CLC-E. Besides, CLC-A obtained nearly half the overhead in area and power and about 27% less delay when compared to CLC-E, which is a significant reduction in the synthesis cost.