Symposium on Integrated Circuits and Systems Design (SBCCI)
Sociedade Brasileira de Computação - SBC
A Machine Learning Approach to Accelerating DSE of Reconfigurable Accelerator Systems
Reconfigurable hardware accelerators (RAs) have become a frequent choice in embedded systems design to meet the performance demand of current embedded applications. However; answering when the combination of general purpose processors (GPPs) and RAs can provide the expected performance at the additional area and energy cost demands an extensive design space exploration. In this scenario when varying microarchitectural characteristics of both GPPs and RAs; one can easily reach million combinations. Evaluating one of these solutions through hardware synthesis is an extremely costly task. And even the use of high-level simulation tools as alternative does not allow simulating all solutions and meeting time-to-market. In this work; we propose the use of predictive models based on machine learning algorithms to simplify and speed up the design space exploration process of GPPs with RAs. In our case study we combine a superscalar processor and a Coarse-Grained Reconfigurable Architecture. Additionally; considering the accuracy of the prediction; we investigate ten different algorithms by comparing their error prediction rate. In this investigation; we were able to achieve an error prediction rate bellow 2% on average and reduce the time for exploring the design space up to 33× when comparing with a scenario that uses a high-level simulation tool.
A CMOS Analog Two-Layer Full Signal Range Cellular Neural Network for Image Filtering
This work presents the training and realization of a CMOS analog two-layer FSR CNN obtained through the extension of an existing one-layer version. A genetic algorithm has been developed for the learning process and has been applied to the determination of templates parameters in a gray-scale image filtering task. Networks implementing first order Butterworth spatial filters have been simulated and the results are compared to its ideal model and FFT computations; allowing to validate the proposed learning process and circuit applicability.
Design Space Exploration of a Reconfigurable Accelerator in a Heterogeneous Multicore
Energy-efficiency has become one of the most important characteristics in system design, especially in mobile devices. However, keeping the energy-efficiency while maintaining the performance in applications with different demand profiles is challenging. In order to meet the distinct application’s requirement, single-ISA heterogeneous multicore systems have been proposed, such as ARM’s big.LITTLE. Despite these systems offer different micro-architectural cores to meet the application’s demands, only a fixed number of core types are available, limiting the system adaptability. Coarse-Grained Reconfigurable Architectures (CGRA) are highly programmable accelerators and have been successfully used to provide run-time adaptability in single-core systems. This work proposes to integrate ATHENA, a transparent CGRA, to a heterogeneous multicore system in order to improve the system adaptability. A design space exploration is carried out, by changing the number of functional units available in ATHENA, to evaluate distinct energy-performance tradeoffs. Additionally, the area costs introduced by ATHENA are also evaluated. The results show that the most energy-efficient version of ATHENA improves the performance of a low-energy core in 35% while consuming 21.90% less energy, on average, introducing only 13.68% of area overhead. The ATHENA also improves the performance of the high-performance core in 42%, on average, than the standalone high-performance core.
Event-Based CMOS Image Sensor with Shared DVS Module for Pixel Area Reduction
In event-based image sensors, each pixel works asynchronously and generates an event whenever a luminance change is detected by the dynamic vision sensor (DVS). The drawback of the event-based image sensors is the amount of circuitry necessary inside the pixel. The proposed imager has the goal of reducing the area of the asynchronous time-based image sensor (ATIS), while maintaining the main advantages of this sensor: high dynamic range and low data rate transfer. In order to reduce the pixel area, we propose sharing the DVS among four capture circuits. The DVS is a complex circuit which comprises a photodiode, two capacitors and 26 transistors. By sharing the DVS, the number of components of a pixel is reduced by 30%. System-level simulations show that sharing the DVS yields little impact in image quality. Electrical simulations results from the ATIS schematic diagram in a 0.35 μm technology are also presented, considering DVS sharing, when all photocurrents of the block are the same and when one of the four photocurrents is different.
Synthesis and Optimization of Majority Expressions through a Mathematical Model
In this paper, the 3MS (Majority Math Model Solver) algorithm is proposed for use in the optimization of majority logic circuits. The new proposed algorithm receives a sequence of binary numbers as input, representing truth tables with a minimum of 3 and a maximum of 8 variables, and returns an optimized majority function that covers the same minterms. Key in this approach is the formulation of constraints that encode a majority logic problem into a mathematical optimization problem. The resulting set of constraints is then applied to an optimization solver and the results are translated into the output majority function. As cost criteria the minimization of levels is prioritized, followed by the minimization of gates, inverters and gate inputs. The 3MS algorithm was evaluated based on a comparison with the state-of-the-art exact synthesis for majority-of-three networks, which considers the number of levels and gates as cost criteria. Since the 3MS considers two additional cost criterias, the goal of the algorithm is to generate functions that are also exact in relation to the number of levels and gates, but uses fewer inverters and gate inputs. Simulation studies have shown that the 3MS is able to further improve 79% of all 77,292 compared functions, and achieves equal results for the remaining 21%.
Hardware Accelerator for Shapelet Distance Computation in Time-Series Classification
Time-series classification has several important real-world applications and shapelet-based methods have emerged as highly attractive tools for this task. They are appropriate to search for time-series subsequences with high discriminative power among classes. Although these algorithms are accurate and interpretable, the task of measuring local shape similarity results in heavy computational burdens, which may limit their applicability. In this paper we address this issue by proposing a hardware accelerator to compute both Z-Score normalization and Euclidean distance. We identify these tasks as hot spots in shapelet-based TSC and propose scalable and parameterizable hardware that is suitable as a dedicated shapelet-distance engine. Results show that the proposed hardware significantly reduces the run time of the shapelet distance computation. The speedup factor increases with the shapelet length, reaching speedups of more than 5 times when compared to a software execution for shapelets with length larger than 100.
Unlocking the Full Potential of Heterogeneous Accelerators by Using a Hybrid Multi-Target Binary Translator
Embedded systems comprise multiple accelerators to exploit both Instruction and Data-Level parallelism, maximizing performance per watt. However, the use of accelerators usually involves changes in the source code, not maintaining binary compatibility and increasing time-to-market. Therefore, Binary Translation (BT) mechanisms emerge as an alternative, since they dynamically detect and transform parts of the application for optimization without needing any prior modification in the code. Nevertheless, the available BT approaches are limited to one single accelerator, which may not always result in the optimal energy-performance trade-off, since parts of an application may have code that will benefit the most from one accelerator or another depending on its available intrinsic parallelism. Given that, this work proposes a Hybrid Multi-target Binary Translator (HMTBT). Our HMTBT is capable of transparently translating code to different accelerators: a CGRA (Coarse-Grained Reconfigurable Architecture) and a NEON engine, and automatically dispatching the translation to the most well-suited one, according to the type of the available parallelism (ILP or DLP) at the moment. HMTBT improves performance by 54% and 76% and saves energy by 15% and 25% when comparing to a BT targeting a CGRA only and another targeting a NEON engine only. We also compare the HMTBT to a system that features both CGRA and NEON BT mechanisms, showing 12% of energy savings and 14% of performance improvements, on average.
Maximizing Throughput-per-Joule of a Hybrid Communication Infrastructure Through a Software-Hardware based DVFS Mechanism
Embedded systems have been demanding massive parallel computing encapsulated inside one single chip. As more cores are integrated into a single chip, higher bandwidth must be available, which conflicts with severe power constraints of embedded devices. Dynamic Voltage and Frequency Scaling techniques have been widely employed in homogeneous communication infrastructures to tune the available throughput of the fabric to best fit the application communication demands. However, homogeneous infrastructures have a restricted number of voltage and frequency pairs due to their uniform fabric shape, which limits the opportunities to maximize power savings. In this work, we propose a software-hardware based DVFS in a Hybrid Communication Infrastructure composed by Bus, Crossbar and NoC to maximize the Throughput-per-Joule. The proposed DVFS approach works at structure-level by adjusting voltage/frequency of each structure depending on the application demands. The proposed DVFS mechanism improves the Throughput-per-Joule (TpJ), on average, in 29% over the Hybrid Structure without DVFS. Moreover, it boosts TpJ gains over Network on Chip fabrics by 23% in scenarios where both fabrics offer the same throughput.
The use of the analog wavelet filter to generate a sinusoidal signal and decompose the TEB signal into its cardiac and respiratory components in implantable cardiac pacemaker systems
A sinusoidal signal generator and signal decomposition filter are presented for use in systems to measure thoracic bioimpedance (TEB) in implantable cardiac pacemakers. The proposed systems use the analog wavelet filter as a base. An analysis of the proposed sinusoidal signal shows that it has a harmonic distortion rate of 1.4% and a spurious free dynamic range (SFDR) of 36.67dB. With the sinusoidal generator applied to a bioimpedance measurement system, the TEB recovery precision was 0.11Ω rms . The new TEB signal decomposer, serves for cardiac and respiratory components, using an TEB decomposer. The results show that TEB decomposer is efficient, even with variations in heart rate. Previous work indicates that the components used in the proposed systems can be implemented in circuits with ultra low energy consumption, which allows the use in implantable systems with pacemakers.
2PSA: An Optimized and Flexible Power-Precision Scalable Adder
Adders are the core of all arithmetic circuits and the proposition of efficient adders, in distinct perspectives, are a constant in the last decades, with a myriad of solutions focusing on a wide variety of applications. The emergence of approximate computing encouraged the development of a new generation of dedicated imprecise adders intending to reduce delay, area, power and/or energy, but none of the proposed solutions is able to support run time definition of distinct power-precision operation points. This article presents the Power-Precision Scalable Adder (2PSA) which is a dynamically configurable power-precision imprecise adder, where the number of power-precision operation points can be configured at design time and each supported power-precision operation point can be changed in run time. The obtained experimental results showed that 2PSA is a fully flexible and efficient imprecise adder, supporting a high variety of power-SNR pairs, as well as a wide range of applications. Considering 8-bit adders, the power-SNR pairs vary from 2%-55dB to 60%-13.75dB, where eight operation points are allowed. Considering 64-bit adders, the power-SNR pairs ranges from 2%-325dB to 60%-16.65dB and 64 operation points are allowed. 2PSA also reached expressive power (from 18% to 73%) and area (from 54% to 73%) savings when compared with non-optimized solutions supporting the same operation points.
Firefly: An Open-source Rocket-based Intermittent Framework
Intermittent systems are ultra-low-power batteryless devices that are increasing in popularity. These systems operate with energy extracted entirely from the environment. Since most environments cannot ensure sufficient and steady power supply conditions, intermittent devices suffer from frequent power outages, where computation is interrupted due to the lack of energy. While numerous works have enabled intermittent computation via many different techniques, there are no versatile and configurable tools that ensure functionality, and rapid development/design space exploration. Therefore, in this paper, we present Firefly, an intermittent open-source framework for developing ultra-low-power devices based on the RISC-V ISA and the Rocket Chip. Firefly enables developers to modify and extend the project to satisfy their preference, i.e., memory technologies, intermittent environment configuration, and hardware modifications. By exploiting the versatility offered by the Firefly framework, we evaluate different memory technologies in an intermittent environment, showing that in many times PCRAM and RRAM will be the best choices to compose the design.
A 0.55-V 0.1oC-Accuracy All-CMOS Temperature Sensor for Implanted Devices
A compact ultra-low power low-voltage all-CMOS temperature sensor for implanted devices is presented. Besides the analog front-end (AFE), the sensor topology incorporates a ring oscillator and a counter. The AFE performs a PWM-based voltage-to-time conversion of a temperature-modulated pulsewidth for the subsequent quantization. A pair of temperature cells delivers both reference and CTAT voltages for pulsewidth modulation. Intended for body-temperature measurements, the sensor is designed according to a standard 0.18μm CMOS, with theoretical analysis backed up by SPICE data over the range [36°C–41°C]. Owing to structurally-alike temperature cores, a design that preserves its reliability across process corners (FF fast-fast, FS fast-slow, SS slow-slow and SF slow-fast) is achieved, making trimming of temperature voltages and frequency unnecessary. The circuit estimated area is 0.003 mm 2 and dissipates typically 365nW, at V DD =0.55V. The temperature elements consume 100pW, which favors multi-channel versions of the sensor. After 2-point calibration, the overall inaccuracy is 0.1°C for TT, FF and SF cases, while 0.2°C and 0.3°C at SS and FS corners, respectively. The approach is easily scalable and therefore suitable to progress into more advanced CMOS nodes.
Characterization of Enclosed Layout Transistors for Analog Applications on a 130nm Technology
Enclosed Layout Transistors (ELT) comprise a feasible design alternative to hardening CMOS circuits against total ionizing dose effects. This design technique significantly reduces the leakage paths produced by trapped charges in the field oxide of regular NMOS devices. This work presents the characterization of several ELT devices designed and fabricated on a 130nm technology aiming at analog applications. Standard (rectangular) transistors with equivalent aspect ratio were also considered for comparison. The experimental data are compared with simulations performed using a commercial design tool, considering the aspect ratio (W/L) extracted from the layout. ELTs with the drain designed both as the inner and outer terminal were characterized and compared. Additionally, in order to improve the achievable aspect ratio range of the square ELTs, parallel and series associations of enclosed devices were implemented as well. According to obtained results, there may be significant differences between the W/L extracted from the design tool and its actual value in the fabricated device. For all enclosed devices, the simulation overestimates the current values. A different pattern regarding the influence of drain location (inner or outer terminal) on current performance is also observed when comparing measured data with simulations. Additionally, associations of ELT showed to be feasible to widen the range of possible aspect ratio of this particular transistor.
Analysis of single-module and cascade molecular analog circuits for approximate computing based on DNA Strand Displacement
Emerging technologies, as DNA computing, promise to help with early diagnosis and disease treatments. For this purpose, molecular circuits design needs to become easier and feasible. Based on previous works, we built arithmetic analog circuits in single and cascade modules of different sizes using DNA Strand Displacement reactions. This paper aims to analyze such circuits for approximate computing. The simulation results showed that the circuit must be specific since its processing capacity (defined by the input range) reduces accuracy and scalability. In adders, the output error decreases when the inputs are close to the maximum, while in subtractors, a pattern was not observed. Moreover, leak reactions compromise the accuracy, especially for the cascade versions. This conclusion indicates that analog single-modules can be a better design alternative.
Performance Comparison of High-Speed Dual Modulus Prescalers using Metaheuristics Sizing/Optimization
The performance comparison of High-Speed Dual Modulus Prescalers is investigated. To implement the comparison, five topologies of divide-by-2/3 are sized/optimized through metaheuristics in 180 nm and 65 nm CMOS technologies. In the optimization process, the speed, the power consumption, the total gate area of the clocked transistors, and the total circuit area are checked. Optimized designs, for the 65 nm technology, have achieved power consumption lower than 3.0 uW/GHz for operation frequencies as high as 8.0 GHz, and operation frequency as high as 14 GHz with power consumption lower than 8.0 uW/GHz. The application of metaheuristics allowed a fair comparison between topologies, making it possible to determine which topologies are the most efficient in terms of speed and power consumption.
Low-Voltage Dynamic Comparator with Bulk-Driven Floating Inverter Amplifier
This work presents a low voltage dynamic comparator for low-power ADC applications. The dynamic comparator uses a pre-amplifier powered by a floating reservoir capacitor and bulk-driven structure. The latch stage is done by a simple circuit to reduce the total voltage overhead necessary to define the logic levels and uses a charge sharing technique in order to reduce the energy consumption per conversion. The floating reservoir capacitor powered pre-amplifier reduces the impacts of global process variability and improves the input common-mode voltage performance. The bulk-driven structure lowers the threshold voltages of the pre-amplifier transistors at the sampling phase. Such structure also works as a positive feedback signal during the comparison phase to provide extra transconductance. The proposed dynamic comparator is designed and simulated in 28nm CMOS technology and reaches a performance suitable for 8 bits ADCs working with 600mV power supply. The dynamic comparator achieves 380μV input-referred noise, while consuming only 40 fJ per comparison and having a nominal delay of 2.26ns.
Multiple-objective Management based on a Distributed SDN Architecture for Many-cores
The management of many-core systems is evolving to meet multiple objectives simultaneously. The Software-Defined Networking (SDN) has benefits explored in recent works that point it as a candidate to address this requirement at the communication level, at the same time that promotes management flexibility and reduced hardware complexity. Most of the research in SDN for many-cores assumes a centralized SDN (C-SDN) Controller and single-objective management This work proposes multi-objective management based on a distributed SDN (D-SDN) architecture (SELF-SDN). The management is self-adaptive, addressing QoS and fault-tolerance simultaneously at the communication level. Experiments targeting QoS show that SELF-SDN provides a reduced amount of latency misses (−67%) and fast reaction time (−49.6%) to recover the QoS constraints compared to a C-SDN approach. Fault-tolerance experiments highlight the simplicity of the SDN paradigm to recover from faults in the NoC, not requiring additional hardware. Results related to multi-objective management demonstrate the fast reaction time of SELF-SDN to recover the communication latency faced to QoS loss and faults, reducing, on average, in 43% the reaction time compared to a C-SDN approach.
Mapping and Migration Strategies for Thermal Management in Many-Core Systems
New technology nodes enable the integration of billions of transistors in a small silicon area by replicating identical structures, resulting in many-core systems. However, power density may limit the amount of energy the system can consume. A many-core at its maximum performance may lead to safe temperature violations and, consequently, result in reliability issues. Dynamic Thermal Management (DTM) techniques proposals guarantee that many-core systems run at good performance without compromising reliability. In this paper, we review recent DTM works, discussing their limitations, and propose new heuristics for thermal-aware application mapping and migration, using a hardware accelerator that enables temperature monitoring on systems with a large number of processing elements. Results show that using straightforward heuristics, with reactive actions based on runtime temperature monitoring, reduce the peak temperature in high workload scenarios (6.8%), and improve thermal distribution significantly on a large (8×8) many-core system.
CLC-A: An Adaptive Implementation of the Column Line Code (CLC) ECC
Column-Line-Code (CLC) is an Error Correction Code (ECC) designed to correct multiple errors in memory devices for critical applications. CLC has originally two decoder modes: CLC Standard (CLC-S) and CLC Extended (CLC-E). CLC-E presents higher efficacy in correcting multiple errors, although consuming more area, dissipating more power, and presenting higher delay than CLC-S, which impacts the overall system performance. This paper proposes the CLC Adaptive (CLC-A), an alternative CLC mode that introduces a Syndrome Analyzer circuit, allowing the system to decide if a second error checking is required to correct the data. The experimental results show that CLC-A reaches higher error correction rates than CLC-S and similar values of CLC-E. Besides, CLC-A obtained nearly half the overhead in area and power and about 27% less delay when compared to CLC-E, which is a significant reduction in the synthesis cost.
Modeling and Optimization of a Microprobe Detector for Area and Yield Improvement
Common physical attacks in integrated circuits make use of microprobes to sense information in specific bus lines. It can be mitigated with additional built-in circuitry to detect deviations in the expected capacitance of the bus lines caused by these attacking probes. The strategy is to convert capacitance deviations into delay deviations, followed by time-to-digital conversion to provide a signature that is used to identify a probe attack. However, the sensitivity to delay deviation is highly related to individual sizes of elements that compose the protecting circuit. In this paper, a multi-objective optimization-based methodology is applied to optimize the required silicon area as well as the robustness and parametric manufacturing yield of a microprobe detector. We present the required computational modeling of the circuit optimization objectives and constraints for a successful application of optimization methods. Results show that this approach reduces the required circuit gate area up to 50% compared to manual sizing, while guaranteeing high manufacturing yield.
Evaluation of Cache-Based Memory Hierarchy for Video Decoding Applications
The intra-frame and inter-frame prediction techniques for video encoding, although not exclusively, are key factors in the architectural design of many codec specifications. Adding to the intense exploitation of the processing resources, video codecs carry a very significant energy footprint when it comes to the data flow between the main memory and the processing unit. The present work provides an evaluation of the cache and main memory hierarchy taking the perspective of the energy-related resources demanded in order to perform video decoding. This paper considers various encoding configurations, video sequences, and cache memory parameters. Our methodology uses HEVC state-of-the-art codecs as a case study and employs memory architecture and power models to properly evaluate the memory infrastructure efficiency in terms of hit ratios and energy consumption. Beyond the data reuse comparison between HEVC encoder and decoder sides (28% lower hit ratios at the decoder on average), our results demonstrate the poor effectiveness of increasing cache capacity for providing energy and performance expressive improvements, as its resources are increased, in a video decoding scenario: 5%–76% of higher memory energy consumption when the cache capacity is increased, on almost all the cases. In view of this result, the exploration of novel memory organizations seems to be advised towards the optimization of video encoding techniques.
A Novel Single Propagation Path Multimode PA
In this paper a novel configuration of a power amplifier (PA) with a single propagation path is presented. It produces multimode operation by acting on the levels of AC voltages swings of a stacked architecture. The configuration is supported by two main concepts: consecutive voltage amplifications and selecting the operation modes of transistors (as an amplifier or as a switch) via different biasing levels. By combining these concepts, it is possible to select the output power delivered to the load, due to the number of transistors that will operate adding power to the output signal. The concept is tested at 2.4 GHz and on a 130 nm RF CMOS process and obtained post-layout simulation results are reported. The proposed proof of concept has three efficiency profiles, namely: low-power (LP), medium-power (MP) and high-power (HP). At LP mode, it performs a 1 dB output compression point (OCP 1dB ) of 16.8 dBm with a power added efficiency (PAE) of 28.1 %. At MP mode, it performs an OCP 1dB of 18.1 dBm with a PAE of 28.9 %. Lastly, HP mode performs an OCP 1dB of 19.9 dBm with a PAE of 25.7 %.
Directional Intra Frame Prediction Architecture with Edge Filter and Upsampling for AV1 Video Coding
Video compression following the AOMedia Video 1 (AV1) format has become more popular since the bitstream specification launching in 2018. However, although the reference AV1 codec libaom achieves much better compression efficiency in comparison to predecessors, its high computational cost forbids use for real-time compression. To allow for real-time operation, hardware accelerators for the most complex AV1 tools, such as the intra-frame prediction, are required. This paper presents a highly parallelized ASIC solution for the directional intra-frame prediction of AV1, which includes the pre-processing steps of edge filtering and upsampling and the directional intra-frame prediction with support to all nominal angles. The proposed hardware design was synthesized for the TSMC 40nm technology for the target frequency of 476MHz required for real-time operation. This scenario led to a required area of 691.742K gates, a power dissipation of 382.076mW and an energy consumption of 2.047nJ/sample. To the best of the authors’ knowledge, this is the first work published in the literature presenting a hardware solution for the directional intra-frame prediction of AV1, including the pre-filtering stages and the support to all nominal angles.
Evidence of a dynamic fault model in the DICE radiation-hardened cell
Hardware redundancy techniques are routinely used for mitigation purposes in radiation-hardened integrated circuits. Duplication indeed has been proved effective to harden the well known dice memory cell against seus. In this work, we nonetheless report, on simulation basis, the possibility of a dynamic fault mechanism that may turn an set into an error. We also introduce and validate a countermeasure that alleviates this weakness.
Fractional-Order Instrumentation Amplifier Transfer Function for Control Applications
This paper explores a new architecture for a fractional-order instrumentation amplifier for control applications. The proposed architecture provides electronic tuning capability and is reconfigurable. It can be configured as either a classic integer-order or a fractional-order instrumentation amplifier, with appropriate tuning of the parameters that define the characteristics of the components involved. The proposed design can be used as a fundamental building block in the implementation of more complex control systems.
A Novel Fully Integrated ULV SC DC-DC Converter for Indoor Light Energy Harvesting
Indoor energy harvesting using small photovoltaic (PV) cells is still not widely exploited. It can be a solution to supply ultra-low power (ULP) devices for Internet of Things (IoT) applications. However, a PV cell may suffer shading caused by walls, furniture, and human movements. This requires an efficient conversion system that can adapt to voltage variations, demanding a specific adjustable DC-DC converter. The present work aims to propose a fully integrated conversion system for indoor photovoltaic energy harvesting capable to provide a range of voltage conversion ratios (VCRs) suitable for ULP and ultra-low voltage (ULV) applications. The proposed converter is based on a reconfigurable switched-capacitor (SC) topology. A systematic simulation-based methodology for designing the DC-DC converter is presented, including switches and capacitors sizing and operating frequency optimization. Results show that the proposed circuit can obtain 19 different VCRs with an estimated peak efficiency of 94.26%. This is an important step towards a practical self-powered indoor system for IoT applications.
Reducing NoC Energy Consumption Exploring Asynchronous end-to-end GALS Communication
Systems-on-Chip (SoCs) with a large number of cores adopt Networks-on-chip (NoCs) as the communication infrastructure due to its scalability. The complexity to distribute a skew-free synchronous clock signal over the entire chip increases in current fabrication technologies due to the process variability. Thus, designers may choose among fully asynchronous and Globally Asynchronous, Locally Synchronous (GALS) NoCs. This work proposes an intermediate solution. Each Intellectual Property (IP) core may have its clock domain, and the NoC supports both synchronous and asynchronous communication. The NoC has its own clock domain, with the synchronous communication used to establish end-to-end paths. Once the end-to-end path is established, the NoC connects the IPs asynchronously, as wires with repeaters. The message is transmitted using handshake protocol at the source IP frequency. The benefit of the proposal is the reduction in the communication energy consumption (up to 52%). The cost is a latency increase (16% to 30%) and area overhead (4%).
A SystemC profiling framework to improve fixed-point hardware utilization
Common hardware design specifications usually describe the worst case scenario to improve fault tolerance and the quality of the final product. When taken to extreme, this approach can also lead to hardware overestimation, resulting on extra logic which, in real scenarios, may never be exercised. In this paper, we propose a SystemC profiling framework to help developers improve fixed-point hardware utilization by reporting unused bits and providing insights on data usage through the source code. We tested our framework against a set of publicly available synthesizable benchmarks (S2CBench), obtaining improvements in latency and area, demonstrating the potential of this technology. We also show a case study based on a proprietary Digital Signal Processor block that had their configurations tuned, for a year, by a group of specialist designers. According to our analysis, the methodology presented in this paper reduced bit requirements on some intermediate computations as much as 55.6%, reducing the energy consumption by 2.46%.
A 37 nW MOSFET-Only Voltage Reference in 0.13 um CMOS
This work presents the design of a MOS-only voltage reference with nano-watt power consumption. The proposed circuit consists of a threshold voltage monitor circuit cascaded with a high-slope proportional to absolute temperature (PTAT) voltage generator. The operation of the circuit is analytically described and a design methodology is presented. The proposed circuit was designed and simulated in a standard 130 nm CMOS process while consuming just 37 nW under 1.2 V of power supply at room temperature. Simulation results present a 585 mV reference voltage with a typical temperature coefficient (TC) of 10.13 ppm/°C, for a temperature range from −40 to 125 °C, a power supply rejection ratio (PSRR) of −54.41 dB at 100 Hz, and a line sensitivity of 0.071 %/V was found for a supply range from 1 V to 1.8 V. Monte-Carlo simulations are presented to evaluate the sensitivity to fabrication variability. The estimated silicon area is 0.0078 mm 2 .
A Management Technique for Concurrent Access to a Reconfigurable Accelerator
Embedded devices with increasing requirements on performance and severe restrictions on area and power have challenged designers to improve their efficiency. While ASICs are one alternative because of their low power and area, they lack generality and programmability. Reconfigurable architectures, on the other hand, bridge the gap between the benefits brought by specialized hardware and the generality provided by traditional general-purpose processors. Nevertheless, reconfigurable architectures, notably Coarse-Grained Reconfigurable Arrays (CGRAs), many times suffer from under-utilization when the workload consists of wide and diverse applications, as in modern embedded devices. Therefore, this work proposes a time-sharing management technique that enables multicore access to a single CGRA, increasing its efficiency (i.e. the tradeoff between performance and area) when compared to traditional architectures, which have a private CGRA for each core. Our set of experiments shows that our mechanism can achieve performance improvements of up to 2.02x over a traditional multicore system without any accelerator. It also increases efficiency up to 89.73% when compared to traditional reconfigurable systems composed of privately coupled CGRAs, occupying up to 3.92x less area at performance costs of up to 62.61%.
A Hardware Design for 3D-HEVC Depth Intra Skip with Synthesized View Distortion Change
The 3D-HEVC (Three-Dimensional High Efficiency Video Coding) is the state-of-the-art standard to compress three dimensional videos. One of the 3D-HEVC novel tools is the Depth Intra Skip (DIS) which is used to efficiently compress smooth and homogeneous areas of depth maps using four different prediction modes. The decision of which DIS mode will be used to predict the depth map region is done through a distortion metric and at this point the 3D-HEVC also brings a novelty: the use of Synthesized View Distortion Change (SVDC). The SVDC is much more complex than other metrics, however it brings an additional precision to decide the DIS mode, increasing the coding efficiency, and also the objective and subjective qualities of the encoded videos. This paper presents the first published hardware design for the 3D-HEVC DIS using the SVDC metric. The developed hardware was described in VHDL and synthesized for TSMC 40nm library. The design used 11.133k gates and it is able to process two views of 3D HD 1080p videos at 30 frames per second videos with a power dissipation of 4,174 mW.
A Fine-grained Methodology for Accuracy-configurable and Energy-efficient Gaussian Filters Design
Configurable architectures are alternatives to attend the quality and energy requirements of image and video processing dynamically. Together with approximate computing techniques, these approaches allow for energy-efficient digital systems regarding the error-tolerant applications. This paper proposes a fine-grained methodology to deal with multiple power-performance-quality requirements needed in nowadays digital Complementary Metal-Oxide-Semiconductor (CMOS) design. The main objectives can be observed as follows: i) to perform a design-space exploration through the bit-width reduction of the 2D Gaussian filter, ii) to develop approximate 2D Gaussian filter architectures during the design-time which serves as a proof of concept, and iii) to design a run-time accuracy-configurable 2D Gaussian filter accelerator. The application quality analysis is performed by adopting scripts coded in Python language. All the design-time approximate plus the accuracy-configurable architectures were described in Very High-Speed Integrated Circuits Hardware Description Language (VHDL) and synthesized for Application Specific Integrated Circuit (ASIC) implementation. The results for a 65nm cell-based technology show energy per operation reductions ranging from 9.87% to 59% with bit widths ranging from 7 to 3 bits, respectively. The extra hardware components to ensure the run-time configurable behavior implies up to 14% of area increasing.
Energy reduction opportunities in Field-Coupled Nanocomputing Adders
According to the International Roadmap for Devices and Systems, Field-Coupled Nanocomputing devices and reversible computing techniques are promising topics in a beyond CMOS scenario. In this work, we investigate the application of both subjects in Adders. Precisely, we analyze the energy reduction opportunities in FCN classical Adder’s topologies (i. e., ripple carry, carry lookahead, and carry lookahead block), applying state-of-the-art partially reversible techniques to them. Our goal is to understand the association between the density of connections and logic gates and the achievable fundamental energy limit reduction. We found that, despite the significant differences in depth and size between the topologies, applying the techniques, their fundamental energy limits are almost the same. Moreover, when energy is a critical concern, energy limits could be reduced by up to 54%.
Performance and Variability Trade-offs of CMOS PTAT Generator Topologies for Voltage Reference Applications
This work presents the analysis, design, and performance evaluation of three usual CMOS proportional to absolute temperature (PTAT) voltage generators, with emphasis on variability effects. Minimization or compensation of the main error sources, such as fabrication variability and intrinsic non-linearities, is an important design challenge required to increase the precision and robustness of a voltage reference. The CMOS PTAT topologies are analytically described and design methodologies for PTAT circuits in subthreshold are presented. The compromises between design conditions and resulting performance are evaluated through simulation for these three PTAT generators, including linearity with temperature, temperature coefficient (TC), and variability impact. Monte-Carlo simulations demonstrated the sensitivity of each topology to fabrication variability, showing that the self-cascode MOSFET structure presents the best accuracy of TC, nominal PTAT voltage, and linearity with temperature.
A Straightforward Methodology for QCA Circuits Design
The complementary metal-oxide-semiconductor (CMOS) has been used as the main technology to design integrated circuits in the last decades. However, this technology is near to its physical limits. This way, several new devices have been proposed for the replacement of the transistors, such as the Field-Coupled Nanocomputing (FCN). Many FCN paradigms are being studied, including quantum-dot cellular automata (QCA) and nanomagnetic logic (NML). This work proposes a new methodology for QCA synthesis, which attaches different logic and physical synthesis tools, filling gaps, and proposing new methods and elements for integration. Experiments show that our methodology enables the synthesis tools to find smaller QCA circuits compared to previous works.
Standalone Rate-Distortion FME Architecture
The high computing complexity of video encoders hinders real-time throughput using a software implementation. This drawback can be amended by implementing hardware accelerators for the most computing-intensive encoder tools to achieve real-time processing while maintaining energy efficiency. In this work, we investigate how approximate and precise versions of the Fractional Motion Estimation (FME), one of the most demanding steps of modern encoders, compare in terms of hardware resources and coding efficiency. To that purpose, we designed a hardware architecture for FME targeting real-time throughput for High Definition (HD) sequences and beyond. This architecture searches over 48 candidates and, unlike most related work, uses 16-bit wide horizontal interpolated samples, which is in compliance with the High Efficiency Video Coding (HEVC) reference software. Also, it integrates all FME required computations, including the rate cost of each candidate block, what makes it a standalone FME accelerator. We analyze the impacts of our design choices in terms of coding efficiency, using software simulations, and in terms of power/energy consumption, using results obtained from standard cell synthesis.
Implementation of Asynchronous Pipelines with QDI Template onto FPGAs Using Commercial Tools
The asynchronous paradigm has unusual characteristics due to the lack of the clock signal, being another option for the design of digital systems. This paradigm has several classes of circuits. The QDI circuit class (Quasi Delay Insensitive) is notable for its robustness and high modularity. In this paper, we propose a new asynchronous architecture in the pipeline style for QDI circuits. Unlike many QDI proposals, this architecture is focused on FPGA (Field Programmable Gated Array) platform. We also present an approach based on the platform of commercial tools aimed at FPGAs. Where through a case study, we investigated the implementation of the QDI pipeline in commercial FPGAs. Despite low throughput and a high area, there is a satisfactory dissipated power and remains with all the robustness properties.
Model and simulation of Warpage in packaged IC strips after Mold Array Process
The residual stress in the different layers of the IC package causes warpage in the device, which can lead to a reduction in productivity and reliability. The stress and deformation are related to the material used for packaging and to the geometry of the packaged device. In this paper, an analytical model for the warpage in MAP-BGA strips is developed, these models are intended to provide a quick warpage estimation after the compression molding process. A Finite Element Method (FEM) of the packaged is presented and the simulation results are compared to the analytical model. Both models are validated against experimental observation of samples strips packaged using compression molding process. A commercial Epoxy Molding Compound (EMC) with different thicknesses and different amounts of silicon dies are used to observe the behavior of the curvature for different packaging design parameters. The behavior of the experimental results fits the models’ predictions. As result, the combination of the simplified model and the Finite Element Analyses (FEA) are an adequate methodology for material selection and process design and to estimate the mechanical behavior of the packaged MAP strip, which can be used to validate the packaged device, reducing the cost of prototyping.
All-digital FPGA-based RF pulsed transmitter with hardware complexity reduction techniques
This paper presents an All-digital RF pulsed transmitter design with hardware complexity reduction techniques for FPGA implementation. A study of the hardware operation frequency limitations of the parallel delta-sigma modulators (DSM) for generating the baseband pulsed signal is presented. Also, the effect of inserting zeros in the DSM time-interleaved implementation on the spectrum of the transmitter output signal is discussed and compared to time-interleaved DSM transmitters with and without complexity reduction techniques. Simulations of an all-digital RF transmitter in Simulink ® of Matlab ® and its FPGA integration were performed in order to compare the performance of the studied transmitter topologies. A simulated SNDR of 51 dBm and 43 dBm were obtained for QAM-64 modulated signal for 1.25 Mbps and 10 Mbps, respectively, operating at 250 MHz of sampling frequency and 4GHz of serialization frequency. Further, by applying the reduction technique the hardware complexity could be shrunk by 10.5%.
A Hardware Accelerator for the Segmentation of Hyperspectral Images
Hyperspectral images (HSIs) contain hundreds of spectral bands that combine spatial characteristics of a scene and are widely used in object identification and classification in various industry and science contexts. However, the processing of HSIs requires high processing power, and one of its compute-intensive tasks is the image segmentation. In this context, this paper presents the development of a first hardware accelerator proposed to speedup a multiresolution algorithm for the segmentation of HSIs. The most computationally expensive step of this algorithm was described in HDL and synthesized to FPGA. Results show that the performance of the hardware accelerator is close to that of a 3.2 GHz PC desktop, spending 20% of the energy consumed by the PC to process a single band.