Transistor-Level Logic Gates Ranking Strategy for Selective Hardening - Silva, Gloria D. Claro da; Schvittz, Rafael B.; Butzen, Paulo F. (Anais do Simpósio Brasileiro de Engenharia de Sistemas Computacionais (SBESC); 2024: Anais do XIV Simpósio Brasileiro de Engenharia de Sistemas Computacionais, 2024)
Application-Specific Integrated Circuits, the core of many embedded systems, are increasingly vulnerable to transient faults due to their nanometer scale, high-frequency and low-voltage operation. Traditional hardening techniques, while effective, often incur significant manufacturing costs and energy consumption. To address this, this work presents a novel method that identifies and targets the most vulnerable circuit blocks based on their transistor structure. This approach offers a efficient and cost-effective alternative to existing selective hardening methods that rely on structural metrics such as logic depth and gate fanout. The proposed ranking methodologies demonstrate a substantial potential for improving circuit reliability, with an average Mean Time Between Failures increase of 29% compared to traditional approaches. This technique can be seamlessly incorporated into existing reliability optimization workflows, providing a valuable tool for designers seeking to optimize the performance and reliability trade-off in circuit design.