Parallelism Level Analysis of Binary Field Multiplication on FPGAs - Farias, Luckas A.; Albertini, Bruno C.; Barreto, Paulo S. L. M. (Anais do Simpósio Brasileiro de Engenharia de Sistemas Computacionais (SBESC); 2015: Anais do V Simpósio Brasileiro de Engenharia de Sistemas Computacionais, 2015)
This work describes a pipelined architecture targeting FPGA binary field multiplication. It comprises a generic real time crypto coprocessor able to operate over any field, without a specific vendor specific technology. A performance comparison of this synthesized coprocessor is presented for two major FPGA vendors. The results show that the parallelism levels, often applied as a key point for decision-making, do not affect the area and power consumption in a linear manner, instead, present the local optimal points tied to the technology adopted for deployment.