A Multiple-ISA Reconfigurable Architecture - Capella, Fernanda M.; Brandalero, Marcelo; Fajardo Junior, Jair; Beck, Antonio C. S.; Carro, Luigi (Anais do Simpósio Brasileiro de Engenharia de Sistemas Computacionais (SBESC), 2013)
In these days, every new added hardware feature must not change the underlying instruction set architecture (ISA), in order to avoid adaptation or recompilation of existing code. Nevertheless, this need for compatibility imposes a great number of restrictions to the designers, because it keeps them tied to a specific ISA and all its legacy hardware issues. Considering that the market is mainly dominated by two different ISAs (and, very likely, more to come): x86, used in the general purpose field, and ARM, used in embedded systems, the need for another level (at the Instruction Set Architecture) of adaptability is evident. Binary Translation (BT) appears as a solution for that, since it is capable of transforming binary code so it can be executed on another target architecture. However, BT adds another layer between code and actual execution, therefore bringing huge performance penalties. To overcome this drawback, we propose a new mechanism based on a dynamic two-level binary translation system. The first level translates ARM or X86 code to an intermediate code, which will be optimized by the second level: a dynamic reconfigurable array. In this way, the designer can take advantage of a BT system and program for two different fields of application, without worrying about the underlying architecture. Even though two case studies are presented, the first BT level is easily expandable to other ISAs.