Anais do Simpósio Brasileiro de Engenharia de Sistemas Computacionais (SBESC)
Sociedade Brasileira de Computação - SBC
Reconfigurable Agents for Heterogeneous Wireless Sensor Networks
Heterogeneous wireless sensor networks combine static nodes and mobile nodes. These mobile nodes might present a more sophisticated and powerful computation platform if compared to static nodes. UAVs (Unmanned Aircraft Vehicle) can confer mobility feature to a node, as well as offer a powerful computation platform, including reconfigurable hardware as an execution platform alternative. These types of networks enable a vast and interesting spectrum of applications, like area surveillance, public security support, among others. An UAV might join or leave a network, and thereby migration of agents might occur among UAVs. In this scenario, this paper proposes a reconfigurable agent, which is able to be executed as pure software agent, as well as a hardware agent, depending on the available execution environment and application decisions. The proposed architecture for a reconfigurable agent presents the necessary transparency so that the rest of the system is not aware of the agents' nature. Moreover, the system enables a dynamic migration of an agent reconfiguring thereby itself to the target execution environment, in a transparent manner as well. Case studies and results are presented, showing the feasibility and costs related to the architecture proposed.
Passive Monitoring Software Tool for Evaluation of Deployed WirelessHART Networks
Deployment of Wireless Sensor Networks in real-world control and monitoring applications may reveal performance problems caused by several factors. To track down such problems, it is necessary to inspect the conditions of network and nodes after deployment. In this paper, we discuss a monitoring software architecture for inspection of WirelessHART networks. Capture of information is done in a passive way using sniffers deployed in the network area. Messages are decoded, decrypted, filtered and then visualized in a graphic interface. A WirelessHART network was deployed in a laboratory for performance evaluation using the developed tool.
Exploiting Modbus Protocol in Wired and Wireless Multilevel Communication Architecture
This paper proposes an architectural improvement for the Modbus RTU protocol to integrate equipments in industrial automation networks, employing hybrid communication with wired Modbus RTU and wireless IEEE 802.15.4. These environments have different electromagnetic interferences, requiring protocols with noise immunity to varied equipments such as motors and generators. Modbus RTU is a simple and robust master-slave protocol that accepts the integration of a master with up to 247 slaves into a bus topology. In addition, the IEEE 802.15.4 protocol emerged recently as a wireless solution to industrial environments since it allows electromagnetic spectrum evaluation, and the choice of avoiding communications in noise frequencies and decreasing the error rate between packets. The proposed hybrid communication protocol increases control and topological limits imposed by Modbus RTU by enabling a wired/wireless tree-bus topology and master multiplexing. Moreover, the academy-industry cooperation resulted in features implemented in a gateway, whose efficiency is evaluated with practical experiments in different topologies.
Exploratory Study on the Linux OS Jitter
The operating system (OS) Jitter phenomenon has been considered an import and critical factor in high-performance distributed computing. In this paper, we present the results of an experimental study that quantifies the effects of different sources of OS Jitter in the Linux operating system. We use the design of experiments (DOE) method to conduct controlled experiments statistically planned. Different than previous studies, we found that the processor topology, especially regarding the shared processor cache, has the most significant influence in terms of OS Jitter. Also, we found that in order to reduce the impact of OS Jitter on a given application, the number of computational phases in the algorithm is significantly more important than the number of distributed processes or compute nodes.
Device to Assist the Visually Impaired in Reading Printed or Scanned Documents
Individuals with visual impairment have their ability to access information limited by the lack of mass literature in Braille. This paper presents an embedded application to aid the visually impaired that allows reading and writing printed and/or digitized documents. The solution, designated PORTÁCTIL, is a device composed of five modules: (1) electromechanical Braille cells, (2) hand motion sensor, (3) processing unit, (4) wireless communication and (5) power supply. The text, locally stored or received by wireless communication, is translated to Braille and displayed following the movement of the hand of the reader. Thus, reading occurs in the same way as in books written in Braille. The device is powered by rechargeable batteries and is capable of receiving texts from smartphones and tablets through Bluetooth. Some prototypes were built and tested by several visually impaired users. The adaptation was very good as well as the acceptance. Properties such as weight / volume, energy consumption and performance were evaluated and are given in the full text.
JingleOS: An Operating System to Embedded Devices with Language-Based Protection
Language based protection and high-level language virtual machines (JVM, CLR) have solved many problems of portability and dependability. Development of operating systems with these characteristics for embedded systems could enjoy these benefits with the solution of basic problems related to resource consumption and performance. This paper presents the JingleOS, an operating system designed on these concepts for devices with a few kibibytes of RAM and 8 bits microcontrollers. To support the system design, advanced compiler techniques and extensions of the Java programming language were used, in order to allow low-level hardware access and bare metal execution.
The Development of a Methodology with a Tool Support to the Distributed Simulation of Heterogeneous and Complexes Embedded Systems
Nowadays, embedded systems contains a big computational power and consequently a big complexity. It is very common to find different kinds of applications being executed in embedded systems. With this scenario, it is necessary some method and/or tool that allows the simulation of those systems in an efficient and practice way. The goal of this paper is to expose the integration between Ptolemy II and HLA in order to enable the elaboration of one methodology, with a tool support, to model and simulate large scale heterogeneous embedded systems.
Impact on Reliability in the Control-Flow of Programs under Compiler Optimizations
This paper evaluates the impact on reliability in the control-flow of programs that compiler optimizations incur in terms of fault coverage for the Automatic Correction of Control-flow Errors technique. This technique was implemented in the LLVM framework, enabling the automated analysis of programs. In order to evaluate the efficiency of the technique of fault tolerance we performed a series of fault injection experiments using the MiBench benchmark suite as case study, measuring how individual and combined optimizations impact reliability.
Energy Profile Evaluation of a Cyber-Physical System
In Cyber-Physical Systems (CPS) the operation of electromechanical devices is tightly integrated with the embedded computer system. The diversity of components imply in different profiles of energy consumption. Thereby, it becomes useful to use techniques that can manage the energy consumption. In a previous work, this aspect was modeled using a technique that allows estimating the energy consumption of a battery-powered CPS. In this paper we present a practical implementation of such work, where the peripherals of a mobile robotic system are characterized to compose the energy profile of the system. Conducted experiments measured the electrical currents during a planned navigation of the robot. The results confirm the assumptions assumed by the modeling technique, which proposes a relationship between the embedded computer system and the electromechanical devices, i.e., there is a direct relation between the device's activation and the nature of the software task under execution.
Performance and Energy Consumption Analysis of Embedded Applications Based on Android Platform
This paper presents an analysis of embedded applications based on Android Platform. Analyzing performance and energy consumption from different algorithmic versions this work tries to find a performance and energy pattern for the paradigm used in each used algorithm. Thus, the developer can select the best algorithm version for each application based on the requirements. Android is a Linux based mobile operating system developed by Google in conjunction with the Open Handset Alliance. Nowadays, Android is the world's leading smartphone platform. The Android Platform provides a rich development environment (SDK) including an API, development and debug tool and so on. However, during the development process it is necessary to handle with the system functionalities and it must at the same time help the handling of the embedded systems tight constraints, like performance, energy and power. This paper shows some performance and energy consumption results for a set of applications using different algorithmic versions.
Real-Time Dynamic Voltage Scaling for the EPOS Operating System
Several implementations of Real-Time Dynamic Voltage and Frequency Scaling (RT-DVFS) have been made in the last decade. Most of them, however, are adaptations performed over some Linux-based operating system. The real-time support on Linux systems depend on complex modifications of the system kernel and is often not regarded as hard real-time support. This work presents the design and implementation of the DVFS support for the hard real-time schedulers of EPOS (Embedded Parallel Operating System) -- an application-driven operating system designed to support embedded applications. The design presented here supports the insertion of RT-DVFS heuristics into the system schedulers in a loosely-coupled fashion. The design is implemented in EPOS and evaluated in a XScale processor. Effectiveness of the RT-DVFS heuristic is assessed by implementing two classic RT-DVFS algorithms that were proposed as extensions to the Earliest Deadline First scheduler.
Power Reduction on Embedded Systems Achieved by a Synchronous Finite State Machine Design Technique
Embedded applications that can be modeled as a Synchronous Finite State Machine are prone to a significant reduction in energy consumption when a very straightforward implementation approach is used. The potential for energy consumption reduction is highly dependent of the clock of the Synchronous Finite State Machine. Although the method is limited to synchronous FSM applications the benefits are worth the effort to attempt this modeling approach. The implementation requires only a timer (hardware timer or RTOS timer) that provides the clock of the Synchronous FSM. The energy reduction is obtained by changing the state of the processor to a low power state.
A LLVM Based Development Environment for Embedded Systems Software Targeting the RISCO Processor
In this paper we describe the design and implementation of a compilation and code analysis toolchain for embedded systems software targeting the RISCO processor, using the LLVM project. Small systems embedded in a larger device are by far the most common kind of computational system in use today, deployed in various types of equipments. Because of their nature, an embedded system presents interesting size, efficiency and energy consumption restrictions, among others, that impose unique challenges on a project. In that scenario, the RISCO processor, a RISC architecture similar to MIPS, was created as a simple, efficient, processor that could prove to be a practical alternative to the available commercial options in its price range. The toolchain we developed permit the development, simulation and analysis of software in C and C++ for the RISCO platform, with open source tools. Besides compiling and executing high level code, the environment supports emitting control flow graphs for each module, enabling further analysis. As a case study on using CFGs and generated machine code information we developed a worst case execution time analysis tool for RISCO code. We discuss the scope of the tools, the design decisions involved in the development of the compilation and analysis system, and the results obtained through testing.
A Model to Calculate Exact End-to-End Delay of Sporadic Flows on AFDX Network Using Mathematical Programming
Avionics Full DupleX (AFDX) Switched Ethernet technology provides a deterministic network to avionics context. Guarantees on worst-case end-to-end (ETE) communication delays are required for certification purposes. This paper identifies the worst-case ETE analysis as an optimization problem and proposes a mathematical programming approach to calculate an exact worst-case delay and the corresponding scenario. It allows to significantly increase the size of the configuration for which an exact worst-case can be determined. The approach considers a set of sporadic flows with no assumption concerning the arrival time of packets.
Analyzing the Performance of an Externally Journaled Filesystem
Journaling is a common technique used by current filesystems to ensure data consistency in face of a crash. Because the journal is often stored as a file within the filesystem, journal and fixed-position writes are likely to compete for disk bandwidth, posing a considerable overhead to the storage system. In order to isolate journal and fixed-position traffic, some filesytems allow the journal to be stored in an external device, thereby allowing the exploitation of parallelism and increasing the spatial locality. In this paper we analyze the performance of an externally journaled filesystem under different scenarios and journaling modes and compare it to a traditional journaled filesystem. We found that ordered and writeback journaling modes in an external device can obtain about 40% of performance improvement in a mail server workload if compared to a traditional journaled filesystem; in addition, we also observed that data journaling mode can provide substantial performance gains under very specific workloads.
A Comprehensive Complexity Analysis of User-Level Memory Allocator Algorithms
Memory allocations are one of the most frequently used operations in computer programs. The performance of memory allocation operations is a critical factor in software design; however, it is very often neglected. In this paper, we present a comprehensive complexity analysis of widely adopted user-level memory allocator algorithms. We consider time and space complexity, as well as the allocator overhead. The results show that the Ptmalloc family of memory allocator algorithms outperformed all other investigated allocators in terms of theoretical time complexity and space overhead. All allocators showed the same space complexity.
Natural Landmark Tracking Method to Support UAV Navigation over Rain Forest Areas
Field application of unmanned aerials systems (UASs) have increased in the last decade, with special focus on missions in which there is any kind of risk for the crew. However, in some situations the lack of onboard pilots makes the mission execution a very difficult task. As an example one has long endurance missions over rain forest, and glacial areas, due to the uniform patterns. In this scenario an embedded vision system plays a critical role on both remotely operated and autonomous navigation modes. This paper presents an approach towards a vision system model able to track landmarks in forest areas, as a navigation support for UASs. This system consists of two main steps: (1) multiresolution decomposition and nonrelevant features suppression techniques based on wavelet; and (2) automatic control points identification and matching for sensed video frame and reference image. Preliminary results demonstrated that this model can correctly track a sequence of natural landmarks while suppressing nonrelevant features.
Early Verification of Embedded Systems: Testing Automation for UML Models
It is widely known that errors discovered in advanced stages of a project are expensive to fix. Therefore, it is important to look for errors as soon as possible within the design cycle. This work addresses the early verification of embedded and real-time systems based on testing the behavior specified in the high-level specifications. A tool to automate the execution of test cases on UML models is presented. Its initial goal is to support the engineers in detecting errors on the system behavior before the implementation phase. The engineers specify a set of test cases, describing: runtime scenarios; behaviors to be tested along with their input; and the expected results. The tool executes automatically each test case, reporting its success/failure as well as the obtained results. The proposed approach has been evaluated by means of a case study representing a real-world embedded system application. The achieved results demonstrate that it is feasible to test the system behavior even though when the implementation is still not available.
Request Batching Self-Configuration in Byzantine Fault-Tolerant Replication
Replication techniques that tolerate byzantine failures have been applied in distributed computing to cope with hostile environments in which system components may fail due to malicious or natural causes (e.g., intrusions). From the seminal work of Lamport, Pease and Shostak on Byzantine Generals, in 1982, Castro and Liskov proposed in 1999 a successful solution, named PBFT, which overcomes performance drawbacks of previous ones, based on a number of protocol optimizations, including the use of request batching. Such a work motivated several other works as extension of the PBFT protocol, improving PBFT performance in certain computing environment conditions. In these solutions, which we call PBFT-family protocols, the tuning of the request batching parameters are realized in design time. However, such configuration may not yield the desired performance in dynamic distributed systems where the underlying characteristics change dynamically (e.g., workload, channel QoS, network topology, etc.). To answer to this challenge, this paper proposes an innovative solution to the dynamic configuration of batching parameters inspired on feedback control theory. In order to evaluate its efficiency, the proposed solution is simulated in various scenarios and compared with the original version used in the PBFT-family protocols.
Sufficient Schedulability Tests for EDF-Scheduled Real-Time Systems under Interference of a High Priority Task
We provide four new schedulability tests for a scheduling model according to which there is a high priority task concurrently executed with a set of EDF-scheduled tasks. All tests are proved correct and have their performance evaluated by simulation.
A Study about New Variations for the Spin-Based Multiprocessor Priority Ceiling Protocol
The objective of this paper is to propose spin-based (busy waiting in case of blocking) variations for the Multiprocessor Priority Ceiling Protocol. The variations are compared with existing protocols for the same system model, which is partitioned scheduling and fixed priority, as the Flexible Multiprocessor Locking Protocol. The proposed variations simplify some characteristics, such implementation or reducing the number of processors needed to schedule synthetic sets of tasks, as used in this work.
Schedulability Analysis of Sporadic Messages in the FlexRay Dynamic Segment
FlexRay is a communication protocol heavily promoted as the future de facto standard for automotive systems. A major challenge associated with the design of FlexRay systems is the response time analysis of sporadic messages transmitted in the dynamic segment, a problem that has been shown to be a combinatorial problem. Although there are several methods available to make this analysis, they mainly rely on optimization techniques such as Integer Linear Programming (ILP), or use the Real-Time Calculus (RTC) framework. In this work we propose a method with pseudo-polynomial complexity to derive an upper bound for sporadic messages transmitted in the dynamic segment. We assess the performance of the proposed method comparing it with state-of-the-art methods available in the literature.
System-Level Verification of Embedded Operating Systems Components
The increasing complexity of embedded operating systems is pushing their design to System-Level, leading to the convergence between software and hardware. In such scenario, it is highly desirable to verify system properties formally, regardless of whether their components are going to be implemented in software or hardware. In this paper, we introduce an approach to verify functional correctness and safety properties of embedded operating system components formally and at System-Level. In order to demonstrate our approach, we present a scheduler of an embedded operating system showing that such scheduler follows its specification regardless of the domain it is instantiated. The verified code was subsequently compiled using GCC yielding a software instance and using CatapultC yielding a hardware instance of the scheduler.
Abstraction Techniques for Compositional State-Based Scheduling Analysis
Nowadays, most embedded safety critical systems have to work in a timely manner in order to deliver desired services. In such timed systems not only ordering of events but timing properties are relevant for correctness and performance. In order to be safe and reliable, it is important to have rigorous analysis techniques of timing-dependent (state) behavior. Classical scheduling approaches consider only the system behavior stateless. Especially for safety critical systems this is not sufficient as the state space gives important information of the system which has to be considered by analysis approaches. Our approach for scheduling analysis combines analytical and model checking methods. We consider not only critical instances but the full state space for analysis, where all inter-leavings and task dependencies are preserved. For this, the state space of the entire system architecture is constructed with the aid of input event streams for tasks, and the known behavior of the scheduler of each resource. Based on the state space response times can be determined, and safety properties can be verified by means of reachability checks. As this approach alone is not scalable we present abstraction techniques based on determining output event streams for each resource. For this we exploit well known analytical methods for scheduling analysis. These methods typically abstracts from all inter-leavings leading to very pessimistic results. In this work we present an abstraction technique that is relevant if multiple activations of one task can occur. This technique lies in the middle of both approaches mentioned above.
A Methodology to Adapt Data Path Architectures to a MIPS-1 Model
MIPS (Microprocessor without Interlocked Pipeline Stages) is an Instruction Set Architecture used in applications such as computers, routers, game consoles and various embedded systems. Among the advantages of this pattern, it could be cited the variety of free software such as compilers and simulators. This paper shows a methodology required to adapt other architectures to use a MIPS-1 instruction set without significant increase in chip area and power dissipation. This methodology was applied in two case studies, which architectures at different complexity levels data paths will be adapted to a new model.
Partitioning Algorithms Analysis for Heterogeneous NoC Based MPSoC
Several new applications have high complexity degree, requiring high processing rate and memory usage. Multiprocessor System-on-Chip (MPSoC) is a promising architecture to fulfill these requirements, due to its high parallelism that enables several tasks been executed at the same time. One problem in current heterogeneous MPSoC design is application's tasks partitioning aiming energy consumption minimization and load balance. In order to optimize partition problems, many algorithms have been applied to generate quality solutions. This work aims to analyze and compare stochastic and heuristic partitioning algorithms for obtaining low energy consumption and load balance when applied to tasks partitioning onto heterogeneous MPSoC.
A Model Driven Approach for Android Applications Development
The mobile application development industry is increasingly growing up due to the intensive use of applications in mobile devices, most of them running Android Operating System. However, developing applications for mobile platforms demands additional worries such as code efficiency, interaction with device resources, as well as short time-to-market. Model-driven Engineering (MDE) combined with UML, as already used in software engineering, could provide abstraction and automation for mobile software developers. To support that, adequate tools and approaches are required. This paper presents a MDE approach for Android applications development, which includes UML-based modeling and code generation in order to facilitate and accelerate the development of mobile applications.
Towards an Efficient Memory Architecture for Video Decoding Systems
Multimedia applications are known to use large amounts of memory. The video modules need also high throughput memory port for coding and decoding high resolution video sequences. The design of a multimedia System-on-Chip (SoC) could implement embedded block RAMs but it is much more cost-effective to use a single external memory at the expense of a multichannel memory controller. This paper presents the design and implementation of an efficient memory hierarchy for a Set-Top Box (STB) SoC with a video decoder. To use efficiently the Double Data Rate (DDR) external memory it must be accessed in burst mode whenever possible. In this paper we develop an analysis and implementation of a four level memory hierarchy targeting data latency reduction and bandwidth optimization of the memory port. The case study is DDR2 SDRAM memory used as the main system video memory in a digital television set-top box implemented on a Virtex-5 FPGA. This paper presents the architecture of the system and shows that the memory hierarchy efficiently uses the DDR characteristics while serving four client processes. The proposed memory architecture can reduce data latency in 78% when compared to a direct demand-access procedure.
An Efficient Mutual Exclusion Algorithm for Redundant Resources in Distributed Operating Systems
Increasing demand for distributed applications raises the need for more reliable control of shared resources among distributed processes. Because of the inherent redundancy of distributed systems, algorithms for critical section access must consider not only the shared resource but also the possibility of redundancy of such a resource. These algorithms are thus known as distributed k-mutex since they control access to k versions of the same shared resource. The inherent uncertainties of distributed systems, like unbounded message transfer delay and the difficulty to detect failures, make the distributed k-mutex problem hard to solve. In this paper, we present a k-mutex algorithm that runs under the partitioned synchronous model, which have recently been formalized, which guarantee liveness (termination) without being restrictive as those conventional solutions of synchronous systems. We complement the presentation of our algorithm with related correctness proofs and simulations that show the efficacy of the proposed solution.
(m,k)-Gur Game: Exploiting Message Discards in Order to Increase the Lifetime and Spatial Diversity in Autonomic Wireless Sensor Networks
The main concern in Wireless Sensor Networks (WSN) algorithms and protocols are the energy consumption. Thus, the WSN lifetime is one of the most important metric used to measure the performance of the WSN approaches. Another important metric is the WSN spatial coverage, where the main goal is to obtain sensed data in a uniform way. This paper has proposed an approach called (m,k)-Gur Game that aims a trade-off between quality of service and the increasement of spatial coverage diversity. Simulation results have shown the effectiveness of this approach.
Development of a Low Cost Programmable Logic Controller
Some Brazilian regions have an agricultural vocation and are undergoing on a significant industrialization process, which is mainly caused by the installation of biofuel industries. Therefore, demand for agricultural and industrial automation will be great in the next years. The aim of this study is to develop a low cost small module (hardware card), for use in the automation of simple machines and equipments. This programmable logic controller (PLC) will be part of an open platform that also contains a free software tool for programming PLC in C language, and an online tutorial with detailed instructions about building and programming the system. Thus, students and professionals can automate machinery and equipment in a simple and low cost way. This article shows the electronic design of the PLC, its programming and tests results of the breadboard setup.
SICXE: Improving Experience with Didactic Processors
This paper presents the design, hardware description and test of SICXE processor, as well as a development environment and simulation tools for this architecture. Based on SIC processor, SICXE is a didactic 32-bit RISC that offers integer ALU, floating-point ALU, interrupts, addressing up to 4GB of program memory, programmed I/O based, DMA-based I/O and also supports a simple operating system. The physical model proposed fit in a compact design, operating at frequencies above 50 MHz and may compose larger projects of embedded systems. This entire software and hardware environment also may be applied for university courses in disciplines such as computer architecture, operating systems, system software and compilers.
A Complete H.264 Motion Estimation Architecture
H.264 is the state of the art regarding video compression standards. One of its main compression tools is motion estimation with fractional motion support. Although it is the tool that offers the best gain on data compression, it also requires a lot of computation power. The motion estimation also requires a very high bandwidth with the external memory to perform its operations. In this paper, we present a complete motion estimation architecture that reduces memory bandwidth and is capable of performing full, half and quarter pixel precision refinement. Results show that the proposed architecture can achieve a display rate of 30 frames per second for HD 720p resolution with an operation frequency of 102 MHz.
Cache Preemption Related Delay Accounting via Static Analysis and Functional Simulation
Cache memory related preemption delay causes large variations of the task execution time and tools that perform WCET static code analysis usually do not consider this behavior. The additional cache delays are usually solved by cache partitioning between tasks or they are incorporated in the schedulability analysis equations. This paper estimates the cache preemption delay of a task in two steps: task static analysis for the instruction cache and functional simulation for the data cache. Both steps are used to track the memory references. After that, we estimate which cache blocks may actually cause additional cache faults in a preemption. Due to the use of functional simulation, the calculated cache preemption delay is not the worst case, but this technique does not rely on WCET tools nor the real hardware. After this analysis, we determine the cost of preemption at each point of the program more accurately.
Time Synchronization at OS Level Using the IEEE 1588 Protocol
Time Synchronization is a pertinent field of study to fulfill the OS requirements in many distributed applications. In this work, we implemented the IEEE 1588 protocol - Precision Time Protocol - for the EPOS operating system to deliver the clock time among the network. For test purposes, we choose a topology consisted of one master clock and another slave clock. We made two configurations: one in which we have two previously synchronized clocks, to evaluate their behavior among time after some synchronizations. On the other configuration, we delayed the slave clock in some hours and analysed the behavior of the protocol after some iterations. With the results obtained we can ensure the viability of the protocol implementation to the EPOS operating system and consequently to embedded systems.
A Context Manager for General-Purpose Operating Systems
Context-Aware Computing aims at making computing systems able to capture context information and to adapt to it, providing context-related services and information to users. Context is any information used to characterize in some sense a person, object, or place of interest for a given user or application. Initial definitions of context-aware computing date from twenty years ago, but until now it was not yet fully made available to end users. This paper proposes a generic model of a context manager for general-purpose operating systems, alongside with its implementation and first evaluation results. This model includes methods for building, storing, and managing contexts, and an API to make such information available to applications and users.
Energy-Aware Technology-Based DVFS Mechanism for the Android Operating System
DVFS is an efficient energy saving technique for processors during program execution time. In this paper, we will focus efforts on 3G and Wi-Fi technologies to evaluate the impact of energy consumption when combined with DVFS mechanism based on the Android operating system. An experimental infrastructure with basis on Samsung's Smartphone was used to evaluate the proposed strategy to reduce energy consumption. Results of the proposed approach was compared with nonoptimized approach and an average reduction about 30% in terms of energy consumption was obtained when compared with performance mode.
RAPTOR-Design: Refactorable Architecture Processor to Optimize Recurrent Design
The growth in embedded systems complexity has created the demand for novel tools which allow rapid systems development and facilitate the designer's management of complexity. Especially since systems must incorporate a variety of often contradictory characteristics, achieving design metrics in short development time is an increasing challenge. This paper presents RAPTOR-Design, a framework for System-on-Chip (SoC) design which incorporates a customizable processor architecture and allows rapid software-to-hardware migration, custom hardware integration in a tightly-coupled fashion and seamless Fault Tolerance (FT) capabilities for FPGA platforms. Impact on design metrics of processor customization, FT-capabilities and custom hardware integration are presented, as well as an overview of the design process using RAPTOR-Design.
Design and Implementation of a Network Centric Appliance Platform
Increasing demands on end-to-end solution performance has lead to a generation of workload optimized systems and appliances, with tightly integrated hardware and software delivering substantial improvements over general purpose architectures. Among the many challenges encountered in designing an appliance, the most complex one is making hardware and software high performance and, at the same time, render the system versatile enough to support as many workloads as possible. This paper provides a high level overview of the design and implementation process of such an appliance architecture, as realized by the IBM PowerEN team. The platform includes new silicon (the PowerEN processor), a novel system level board (Chroma card), system software and development kit, as well as end user applications for different industry domains. The solution has been completely designed by the team, starting from concept, to architecture, to implementation and delivery. The paper describes the most important characteristics of the platform, detailing how these influence its capability of supporting multiple optimized workloads.
High Availability for Critical Services Using Open Software and Virtualization
This article presents a proposal to solve the problem of unavailability of services in the level of the operating systems hosted on virtual machines. The proposal is based on the use of open software in order to attend a demand reported in the literature in which we can find some restricted solutions limited to the level of virtualization.
Building a Node for Wireless Sensor Network Based on Open Source Platform Arduino
The aim of this paper is to develop a node, part of a Wireless Sensor Network (WSN), for application in precision agriculture and family crop. The controlling of sensors use the Arduino Development Platform and the communication among nodes is done by MRF24J40MA, transceiver modules Zigbee. The system comprises a firmware and two plates, one of them for control and communication among the nodes and the other for sensing. Then, this paper and its prospects will allow more effective treatment to the problems such as energy waste, water and agricultural defensives as well as the quantitative and qualitative control, and irrigation processes.
WSN Experiment and a Grid-Based Network Architecture Proposal
This paper presents an experiment using a Wireless Sensor Network (WSN) in a rural area with focus on precision agriculture. The experiment lasted 90 days and during this time several events were analyzed highlighting the quality of the communication and events of the environment that affected the normal operation of the WSN. This experiment was the starting point for the proposition of a communication architecture model applied to WSN based on Grid.
Automation Control Targeting of a Solar Distiller
This study aimed at planning, building and running an automatic solar distiller, whose function is to direct the mirror still in the position that there is a maximum brightness of the capture of the sunlight. The distiller was designed in the style of a cylindrical parabolic solar concentrator developed sheet steel, coated mirrors, modeled on a parabolic structure, with a focus along the copper tube functioning as absorber. In the parameters for the automation of the project were considered the elements of machinery, power electronics and industrial instrumentation. The results for the automation of the solar distiller, satisfied the proposed project, as it was possible to obtain the data necessary to perform the mapping and displacement of the distiller in the direction of sunlight.
A Study of Bluetooth Application for Remote Controlling of Mobile Embedded Systems
This paper presents the development of an application for the operational system Android (Android OS) with the intent of controlling embedded systems via Bluetooth. The system to be operated is a teleoperated vehicle for remote sensoring and environmental damage detection. This prototype remotecontrolled vehicle was developed using the open-source development platform Arduino. This prototype has three wireless communication modules: one for Bluetooth communication, another for Zigbee communication, and the last one is a infra-red signal receiver. The results in laboratory tests and in real application field showed the prototype was successful, referring to its initial objectives, controlling locomotion system and high level human-machine interface.
SCProcessor Builder: A Tool to Create and Simulate Processors in SystemC
This paper presents the SCProcessor Builder that consists on a toolset that enables the modeling and simulation of different processor architecture and behavior. The models are designed using XML language and state machines for the structural and behavior parts respectively. The proposed tool converts the models to SystemC in order to simulate the execution of programs on modeled processors.
Evaluating Dalvik Instructions through Dynamic Analysis of Bytecodes
Android is an operating system for smartphones developed by Google that uses the Dalvik Virtual Machine to ensure compatibility of their applications between platforms that use it. This paper presents the evaluation of Dalvik instructions from the results of dynamic analysis of Dalvik bytecodes. Its objective is the identification of a subgroup of instructions which is responsible for most of the execution time in typical embedded applications. The results show that a few instructions are responsible for most of applications' execution time.