Implementation and Analysis of a Low-Power Heart Rate Prediction Solution Using Hardware Acceleration on the ESP32-S3 Microcontroller - Clevelares, João P. M.; Oliveira, Higor D.; Pacheco, André G. C.; Souza Jr, Luis A.; Villaça, Rodolfo S. (Anais do Seminário Integrado de Software e Hardware (SEMISH), 2026)
This work details the implementation of an accelerometry-based heart-rate estimation system optimized for the ESP32-S3 microcontroller. It leverages PIE-based Single Instruction, Multiple Data (SIMD) extensions via ESP-DSP library to accelerate the pre-processing, training and inference of a continual-learning model. Under a modular FreeRTOS architecture, the system achieved 4.99 µs training latency, requiring less than 1 kB of RAM for the ML model itself. Results show a 30.6% computational performance gain and 8% energy consumption reduction with acceleration enabled. These efficiencies allow race-to-sleep strategies that extend the estimated battery life to 51 days on COTS hardware.