Evaluating Memory Constraints of RISC-V Matrix Accelerators using gem5 - Aquino, Iago C.; Krebs, Casio P.; Wanner, Lucas; Rigo, Sandro (Anais do Simpósio em Sistemas Computacionais de Alto Desempenho (SSCAD); 2025: Anais do XXVI Simpósio em Sistemas Computacionais de Alto DesempenhoDO - 10.5753/sscad.2025.16632, 2025)
Matrix multiplication is a core operation in artificial intelligence workloads, often limited by memory bandwidth in modern computing accelerators. This study explores the architectural integration of a prototype RISC-V matrix extension using the gem5 simulator by modeling various memory hierarchy configurations, ranging from private caches to direct DRAM connections. Results demonstrate that strategic memory hierarchy placement significantly enhances computational throughput and efficiency. Our matrix implementation achieves 1.35x the performance of OpenBLAS using the same architectural state and 87% of the theoretical maximum.