Integration and performance analysis of parallel RISC-V architectures - Krebs, Casio P.; Araujo, Guido; Wanner, Lucas (Anais do Simpósio em Sistemas Computacionais de Alto Desempenho (SSCAD); 2025: Anais do XXVI Simpósio em Sistemas Computacionais de Alto DesempenhoDO - 10.5753/sscad.2025.16672, 2025)
Vector and matrix architectures accelerate workloads by exploiting data-level parallelism and reducing instruction overhead, but using them typically requires manual code changes. This work explores the Hwacha vector coprocessor and Gemmini matrix accelerator, alongside the BOOM superscalar RISC-V core, aiming to automate their activation. The SMR code rewriting tool was extended with libraries for data preparation, movement, and Hwacha/Gemmini activation for GEMV and GEMM. Integrated with Verilator, a simulation environment evaluated performance across seven Polybench kernels. Results show SMR can activate hardware accelerators without modifying the base code, enabling efficient acceleration more easily.