Design and Implementation of the PBIW Instruction Decoder in a Softcore Embedded Processor

• Renan Marks Universidade Federal do Mato Grosso do Sul
• Felipe Araújo Universidade Federal do Mato Grosso do Sul
• Renato Santos Universidade Federal do Mato Grosso do Sul
• Felipe Yonehara Universidade Federal do Mato Grosso do Sul
• Ricardo Santos Universidade Federal do Mato Grosso do Sul

Resumo

This paper presents the PBIW (Pattern Based Instruction Word) instruction encoding technique on the \\RVEX embedded soft core processor. The PBIW encoding technique maps the assembly generated by a compiler into an encoding scheme of a target processor. The results obtained shows that the PBIW encoding has a compression ratio ranging from 60.97% to 115.91% among the evaluated programs. The impact of PBIW encoding in the memory access shows significant performance gains since there are improvements in hit ratio up to 58.93%. The PBIW decoder experiments show that the adoption of PBIW decoder circuit shrinks the processor total area in 15% (on average) and dynamic power reduction in 40%. In addition, the PBIW decoder reduces 56% and 52% the dynamic power consumption and the amount of data stored (memory bits of M4K memory blocks) in the instruction memory.

Palavras-chave: Decoding, Encoding, Memory management, Hardware, Field programmable gate arrays, Thumb, Educational institutions