Predicting Hardware Resource Allocation of MVAU Modules in FINN-Generated FPGA Accelerators

• Beatriz Aline Arend UFRGS
• Arthur Ferreira Ely UFRGS
• Fernanda Lima Kastensmidt UFRGS
• Mariana Recamonde-Mendoza UFRGS

DOI: https://doi.org/10.5753/eramiars.2025.16671

Resumo

We propose a method to predict hardware resource allocation of the Matrix Vector Activation Unit (MVAU) in FPGA-based neural network accelerators generated with the FINN framework. A dataset built from synthesis results includes architectural parameters and utilization of LUTs, FFs, RAMBs, and DSPs. Three regression models were evaluated via 10-fold cross-validation. All achieved average R2 above 0.99, with XGBoost yielding the lowest MSE and MAE. Feature importance analysis showed that the Number of Processing Elements and RTL implementation dominate predictions, together contributing nearly 69%. The approach enables accurate and practical resource estimation to support efficient FPGA accelerator design.

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