2PSA: An Optimized and Flexible Power-Precision Scalable Adder

• Roger Porto UFPel/IFSul
• Bruno Zatt UFPel
• Nuno Roma IST/ULisboa
• Luciano Agostini UFPel
• Marcelo Porto UFPel

Resumo

Adders are the core of all arithmetic circuits and the proposition of efficient adders, in distinct perspectives, are a constant in the last decades, with a myriad of solutions focusing on a wide variety of applications. The emergence of approximate computing encouraged the development of a new generation of dedicated imprecise adders intending to reduce delay, area, power and/or energy, but none of the proposed solutions is able to support run time definition of distinct power-precision operation points. This article presents the Power-Precision Scalable Adder (2PSA) which is a dynamically configurable power-precision imprecise adder, where the number of power-precision operation points can be configured at design time and each supported power-precision operation point can be changed in run time. The obtained experimental results showed that 2PSA is a fully flexible and efficient imprecise adder, supporting a high variety of power-SNR pairs, as well as a wide range of applications. Considering 8-bit adders, the power-SNR pairs vary from 2%-55dB to 60%-13.75dB, where eight operation points are allowed. Considering 64-bit adders, the power-SNR pairs ranges from 2%-325dB to 60%-16.65dB and 64 operation points are allowed. 2PSA also reached expressive power (from 18% to 73%) and area (from 54% to 73%) savings when compared with non-optimized solutions supporting the same operation points.

Palavras-chave: Adders, Approximate computing, Delays, Gears, Signal to noise ratio, Batteries, Scalability, arithmetic operators, approximate computing, imprecise adders, low-power design, power efficiency