Performance Comparison of High-Speed Dual Modulus Prescalers using Metaheuristics Sizing/Optimization

• João Navarro USP
• Maximiliam Luppe USP

Resumo

The performance comparison of High-Speed Dual Modulus Prescalers is investigated. To implement the comparison, five topologies of divide-by-2/3 are sized/optimized through metaheuristics in 180 nm and 65 nm CMOS technologies. In the optimization process, the speed, the power consumption, the total gate area of the clocked transistors, and the total circuit area are checked. Optimized designs, for the 65 nm technology, have achieved power consumption lower than 3.0 uW/GHz for operation frequencies as high as 8.0 GHz, and operation frequency as high as 14 GHz with power consumption lower than 8.0 uW/GHz. The application of metaheuristics allowed a fair comparison between topologies, making it possible to determine which topologies are the most efficient in terms of speed and power consumption.

Palavras-chave: Topology, Transistors, Power demand, Integrated circuit modeling, Logic gates, Capacitance, Inverters, dual modulus prescaler, E-TSPC, low power, high speed, metaheuritcs