Low-Voltage Dynamic Comparator with Bulk-Driven Floating Inverter Amplifier

• Bruno Canal UFRGS
• Hamilton Klimach UFRGS
• Sergio Bampi UFRGS
• Tiago Balen UFRGS

Resumo

This work presents a low voltage dynamic comparator for low-power ADC applications. The dynamic comparator uses a pre-amplifier powered by a floating reservoir capacitor and bulk-driven structure. The latch stage is done by a simple circuit to reduce the total voltage overhead necessary to define the logic levels and uses a charge sharing technique in order to reduce the energy consumption per conversion. The floating reservoir capacitor powered pre-amplifier reduces the impacts of global process variability and improves the input common-mode voltage performance. The bulk-driven structure lowers the threshold voltages of the pre-amplifier transistors at the sampling phase. Such structure also works as a positive feedback signal during the comparison phase to provide extra transconductance. The proposed dynamic comparator is designed and simulated in 28nm CMOS technology and reaches a performance suitable for 8 bits ADCs working with 600mV power supply. The dynamic comparator achieves 380μV input-referred noise, while consuming only 40 fJ per comparison and having a nominal delay of 2.26ns.

Palavras-chave: Latches, Inverters, Transistors, Topology, Transconductance, Capacitors, Reservoirs, dynamic comparator, low-voltage CMOS, low-power, bulk-driven, floating inverter