A Management Technique for Concurrent Access to a Reconfigurable Accelerator

• Raul Silva UFRGS
• Guilherme Korol UFRGS
• Michael Jordan UFRGS
• Marcelo Brandalero Brandenburg University of Technology
• Michael Hübner Brandenburg University of Technology
• Monica Pereira UFRN
• Mateus Beck Rutzig UFSM
• Antonio Carlos Schneider Beck UFRGS

Resumo

Embedded devices with increasing requirements on performance and severe restrictions on area and power have challenged designers to improve their efficiency. While ASICs are one alternative because of their low power and area, they lack generality and programmability. Reconfigurable architectures, on the other hand, bridge the gap between the benefits brought by specialized hardware and the generality provided by traditional general-purpose processors. Nevertheless, reconfigurable architectures, notably Coarse-Grained Reconfigurable Arrays (CGRAs), many times suffer from under-utilization when the workload consists of wide and diverse applications, as in modern embedded devices. Therefore, this work proposes a time-sharing management technique that enables multicore access to a single CGRA, increasing its efficiency (i.e. the tradeoff between performance and area) when compared to traditional architectures, which have a private CGRA for each core. Our set of experiments shows that our mechanism can achieve performance improvements of up to 2.02x over a traditional multicore system without any accelerator. It also increases efficiency up to 89.73% when compared to traditional reconfigurable systems composed of privately coupled CGRAs, occupying up to 3.92x less area at performance costs of up to 62.61%.

Palavras-chave: Multicore processing, Program processors, Acceleration, Fabrics, Performance evaluation, Hardware, CGRA, heterogeneous architectures, multi-core