A Hardware Design for 3D-HEVC Depth Intra Skip with Synthesized View Distortion Change

• Vinicius Borges UFPel
• Murilo Perleberg UFPel
• Vladimir Afonso IFSul
• Marcelo Porto UFPel
• Luciano Agostini UFPel

Resumo

The 3D-HEVC (Three-Dimensional High Efficiency Video Coding) is the state-of-the-art standard to compress three dimensional videos. One of the 3D-HEVC novel tools is the Depth Intra Skip (DIS) which is used to efficiently compress smooth and homogeneous areas of depth maps using four different prediction modes. The decision of which DIS mode will be used to predict the depth map region is done through a distortion metric and at this point the 3D-HEVC also brings a novelty: the use of Synthesized View Distortion Change (SVDC). The SVDC is much more complex than other metrics, however it brings an additional precision to decide the DIS mode, increasing the coding efficiency, and also the objective and subjective qualities of the encoded videos. This paper presents the first published hardware design for the 3D-HEVC DIS using the SVDC metric. The developed hardware was described in VHDL and synthesized for TSMC 40nm library. The design used 11.133k gates and it is able to process two views of 3D HD 1080p videos at 30 frames per second videos with a power dissipation of 4,174 mW.

Palavras-chave: Encoding, Hardware, Distortion, Tools, Three-dimensional displays, Measurement, Filling, 3D-HEVC, Depth Intra Skip, Hardware Design, Synthesized View Distortion Change