Implementation of Asynchronous Pipelines with QDI Template onto FPGAs Using Commercial Tools

• Duarte Oliveira ITA
• Gabriel Duarte ITA
• Nicolly Cardoso ITA
• Gracieth Batista ITA

Resumo

The asynchronous paradigm has unusual characteristics due to the lack of the clock signal, being another option for the design of digital systems. This paradigm has several classes of circuits. The QDI circuit class (Quasi Delay Insensitive) is notable for its robustness and high modularity. In this paper, we propose a new asynchronous architecture in the pipeline style for QDI circuits. Unlike many QDI proposals, this architecture is focused on FPGA (Field Programmable Gated Array) platform. We also present an approach based on the platform of commercial tools aimed at FPGAs. Where through a case study, we investigated the implementation of the QDI pipeline in commercial FPGAs. Despite low throughput and a high area, there is a satisfactory dissipated power and remains with all the robustness properties.

Palavras-chave: Pipelines, Logic gates, Registers, Field programmable gate arrays, Delays, Clocks, Robustness, QDI asynchronous logic, dual-rail code, pipeline