All-digital FPGA-based RF pulsed transmitter with hardware complexity reduction techniques

• Nágila Ribeiro de Menezes USP
• Hugo Daniel Hernandez UFMG
• Dionísio Carvalho USP
• Wilhelmus Van Noije USP

Resumo

This paper presents an All-digital RF pulsed transmitter design with hardware complexity reduction techniques for FPGA implementation. A study of the hardware operation frequency limitations of the parallel delta-sigma modulators (DSM) for generating the baseband pulsed signal is presented. Also, the effect of inserting zeros in the DSM time-interleaved implementation on the spectrum of the transmitter output signal is discussed and compared to time-interleaved DSM transmitters with and without complexity reduction techniques. Simulations of an all-digital RF transmitter in Simulink ® of Matlab ® and its FPGA integration were performed in order to compare the performance of the studied transmitter topologies. A simulated SNDR of 51 dBm and 43 dBm were obtained for QAM-64 modulated signal for 1.25 Mbps and 10 Mbps, respectively, operating at 250 MHz of sampling frequency and 4GHz of serialization frequency. Further, by applying the reduction technique the hardware complexity could be shrunk by 10.5%.

Palavras-chave: Complexity theory, Hardware, Field programmable gate arrays, Frequency modulation, Radio transmitters, Topology, Fully digital transmitter, Delta-Sigma Modulator, Time-interleaved, hardware complexity reduction, zeros insertion