Exploring Heterogeneous Task-Level Parallelism in a BMA Video Coding Application using System-Level Simulation

  • Carlos Michel Betemps UNIPAMPA
  • Mateus Melo UFPel
  • Amir M. Rahmani TU Wien
  • Antonio Miele Politecnico di Milano
  • Nikil Dutt University of California
  • Bruno Zatt UFPel


High abstraction level models can be used within the system-level simulation to allow rapid evaluations of architectural aspects in early Design Space Exploration (DSE) and direct the development decisions. Further, early DSE is of paramount importance in the specification of future Embedded Systems (ES) and its evaluation for applications with high computing demands and energy restrictions. This paper presents the exploration of Heterogeneous Task-Level Parallelism (HTLP) in a Block-Matching Algorithm (BMA) video coding application. HTLP means the creation and execution of simultaneous threads of kernels defined for different types of Processing Elements (PE) - e.g., CPU and GPU - but all for an equal purpose. We employ a BMA implementation as a case study, and its characteristics are used to explore the HTLP - in particular, its kernels for data preparation, SAD (sum of absolute differences) criteria calculation, and SAD values grouping. For the exploration, a system-level simulation framework (SAVE-htlp) is augmented, being able to support the HTLP. In the performed experiments, SAVE-htlp simulates workload and architecture models and explores 22 settings varying the PE type employed during the tasks' execution and the number of concurrent threads for each kernel. Execution time, performance, energy, and power results show HTLP settings overcoming CPU-only ones as well as those with solely GPUs to process its tasks.

Palavras-chave: Heterogeneous Task-level Parallelism, System-level Simulation, Block-Matching Algorithm, Embedded Systems.


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BETEMPS, Carlos Michel; MELO, Mateus; RAHMANI, Amir M. ; MIELE, Antonio; DUTT, Nikil; ZATT, Bruno. Exploring Heterogeneous Task-Level Parallelism in a BMA Video Coding Application using System-Level Simulation. In: SIMPÓSIO BRASILEIRO DE ENGENHARIA DE SISTEMAS COMPUTACIONAIS (SBESC), 8. , 2018, Salvador. Anais [...]. Porto Alegre: Sociedade Brasileira de Computação, 2018 . p. 105-112. ISSN 2237-5430.