Generation of SystemC Simulation Models From Service Level UML Diagrams
Modeling communication of embedded systems at service level, where most of the communication details are abstracted, is mandatory in the initial phase of design in order to decrease design complexity. For that, service level UML profiles have been adopted in recent years for specifying embedded systems. In order to quick validate early system specifications, designers have to write manually simulation models in system level languages like SystemC or SystemVerilog. The problem of these languages is that they do not abstract communication details such as ports and channels. Moreover, designers must add code to enable different execution modes (parallel or sequential) and to implement different communication modes (synchronous or asynchronous services calls). This work generates automatically SystemC simulation models from UML service level models. The generated simulation model comprises all the communication infrastructure (ports, channels and interconnections) and different communication and execution modes. An object recognition embedded system was designed in order to prove the efficacy of the proposed work. Results show that this work reduced significantly design time by generating most of the code of the simulation model.
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