Generation of SystemC Simulation Models From Service Level UML Diagrams
Resumo
Modeling communication of embedded systems at service level, where most of the communication details are abstracted, is mandatory in the initial phase of design in order to decrease design complexity. For that, service level UML profiles have been adopted in recent years for specifying embedded systems. In order to quick validate early system specifications, designers have to write manually simulation models in system level languages like SystemC or SystemVerilog. The problem of these languages is that they do not abstract communication details such as ports and channels. Moreover, designers must add code to enable different execution modes (parallel or sequential) and to implement different communication modes (synchronous or asynchronous services calls). This work generates automatically SystemC simulation models from UML service level models. The generated simulation model comprises all the communication infrastructure (ports, channels and interconnections) and different communication and execution modes. An object recognition embedded system was designed in order to prove the efficacy of the proposed work. Results show that this work reduced significantly design time by generating most of the code of the simulation model.
Referências
Object Management Group (OMG).UML Profile for System on a Chip. https://www.omg.org/spec/SoCP/1.0.1/. Acessed: 04-11-2018
M. Gomes, C. Araújo, A. Sarmento, C. Ceissler, J. Bezerra, D. Farias, “Reducing soc design effort by abstracting communication details using an esl centric service based Uml profile”. In: 9th Microelectronics Students Forum ( SForum 2009), 2009, Natal, Brazil.
A.G. Silva-Filho, F. R. Cordeiro, C. Araújo, A. Sarmento, M. Gomes, E. Barros, M.E. Lima, “An esl approach for energy consumption analysis of cache memories in soc platforms”. International Journal of Reconfigurable Computing (Print), v. 2011, p. 1-12, 2011
K. Svarstad, G. Nicolescu, A.A. Jerraya, “ A model for describing communication between aggregate objects in the specification and design of embedded systems” . Proceedings of the conference on Design, Automation and Test in Europe, p.77-85, March 2001, Munich, Germany.
A. Aziz, F.S. Santos, D. Santos, M. Almeida, E. Barros, “An UML- driven Interface Generation Approach for SoC Design with Synthesizable SystemC Code Generation”. In: IP Based Eletronic System Conference & Exhibition, 2008, Grenoble. IP Based Eletronic System Conference & Exhibition Proceedigns, 2008. p. 31-36
E. Riccobene, P. Scandurra, A. Rosti, S. Bocchio, “ A soc design methodology involving a Uml 2.0 profile for SystemC”. In proceedings of the Design, Automation, And Test In Europe, p.704-709, March 2005, Munich, Germany.
J. Vidal, F. de Lamotte, G. Gogniat, P. Soulard, J.P. Diguet, “A co- design approach for embedded system modeling and code generation with UML and MARTE” . ”. In proceedings of the Design, Automation, And Test In Europe, pp. 226-231, April 2009, Nice, France.
M. Leite, M. A. Wehrmeister, “System-level design based on UML/MARTE for FPGA-based embedded real-time systems” Design Automation for Embedded Systems, June 2016, Volume 20, Issue 2.
F. Boutekkouk, “Automatic SystemC code generation from UML models at early stages of systems on chip design”. International Journal of Computer Applications 8(6):10–17, October 2010.
