HyHeMPS: A Hybrid Communication Infrastructure for MPSoC.

  • Rafael Follmann Faccenda UFSM
  • Mateus Rutzig UFSM
  • Luana Lima de Freitas UFSM

Resumo


The increasing integration of many processing elements inside the same die has been raising the need to create efficient communication infrastructures. Different structures have been exploited to interconnect those elements, such as NoCs, crossbars and buses, each one being commonly employed separately. However, current MPSoCs have faced severe design constraints that must balance area and communication efficiency. This work exploits, over a quantitative analysis, the feasibility of the separate employment of Shared Bus, NoC and Crossbar. Such analysis suggests that the utilization of an one-exclusive infrastructure is not ideal to balance the area and execution time. So, the second contribution of this work is the proposal of HyHeMPS (Hybrid-Hermes Multiprocessor System on chip) which merges the concepts of the three analyzed communication infrastructures (Bus, NoC, Crossbar) in a single platform. Results show that the proposed hybrid infrastructure can be used to balance the on chip communication constraints since it maintains performance of a 4x4 NoC saving up to 25% of chip area.

Palavras-chave: NoC, Communication Infrastructure

Referências

W. J. Dally and B. Towles, “Route packets, not wires: On-chip interconnection networks,” in Design Automation Conference, 2001. Proceedings. IEEE, 2001, pp. 684–689.

S. Lee, M. Yanagisawa, T. Ohtsuki, and N. Togawa, “BusMesh NoC: A novel NoC architecture comprised of bus-based connection and global mesh routers,” in Circuits and Systems (APCCAS), 2010 IEEE Asia Pacific Conference on. IEEE, 2010, pp. 712–715.

P. Zarkesh-Ha, G. B. Bezerra, S. Forrest, and M. Moses, “Hybrid network on chip (HNoC): local buses with a global mesh architecture,” in Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction. ACM, 2010, pp. 9–14.

T.D. Richardson, C. Nicopoulos, D. Park, V. Narayanan, Y. Xie, C. Das, and V. Degalahal, “A hybrid SoC interconnect with dynamic TDMA- based transaction-less buses and on-chip networks,” in VLSI Design, 2006. Held jointly with 5th International Conference on Embedded Systems and Design., 19th International Conference on. IEEE, 2006, pp. 8–pp.

N. Prasad, P. Mukherjee, S. Chattopadhyay, and I. Chakrabarti, “Design and evaluation of ZMesh topology for on-chip interconnection networks,” Journal of Parallel and Distributed Computing, vol. 113, pp. 17–36, 2018.

O. Inam, S. AlKhanjari, and W. Vanderbauwhede, “Shortest path routing algorithm for hierarchical interconnection network-on-chip,” Procedia Computer Science, vol. 56, pp. 409–414, 2015.

K. Cheshmi, S. Mohammadi, D. Versick, D. Tavangarian, and J. Trajkovic, “A clustered GALS NoC architecture with communication-aware mapping,” in Parallel, Distributed and Network-Based Processing (PDP), 2015 23rd Euromicro International Conference on. IEEE, 2015, pp. 425–429.

J. Ax, G. Sievers, J. Daberkow, M. Flasskamp, M. Vohrmann, T. Jungeblut, W. Kelly, M. Porrmann, and U. Rückert, “CoreVA-MPSoC: A many-core architecture with tightly coupled shared and local data memories,” IEEE Transactions on Parallel and Distributed Systems, 2017.

L. Yang, W. Liu, P. Chen, N. Guan, and M. Li, “Task mapping on smart NoC: Contention matters, not the distance,” in Design Automation Conference (DAC), 2017 54th ACM/EDAC/IEEE. IEEE, 2017, pp. 1–6.

M. F. Reza, D. Zhao, and H. Wu, “Task-resource co-allocation for hotspot minimization in heterogeneous many-core NoCs,” in Proceedings of the 26th edition on Great Lakes Symposium on VLSI. ACM, 2016, pp. 137–140.

F. Moraes, N. Calazans, A. Mello, L. Möller, and L. Ost, “HERMES: an infrastructure for low area overhead packet-switching networks on chip,” INTEGRATION, the VLSI journal, vol. 38, no. 1, pp. 69–93, 2004.

M. Mandelli, L. Ost, G. Sassatelli, and F. Moraes, “Trading-off system load and communication in mapping heuristics for improving NoC-based MPSoCs reliability,” in Quality Electronic Design (ISQED), 2015 16th International Symposium on. IEEE, 2015, pp. 392–396
Publicado
06/11/2018
Como Citar

Selecione um Formato
FACCENDA, Rafael Follmann; RUTZIG, Mateus; DE FREITAS, Luana Lima. HyHeMPS: A Hybrid Communication Infrastructure for MPSoC.. In: SIMPÓSIO BRASILEIRO DE ENGENHARIA DE SISTEMAS COMPUTACIONAIS (SBESC), 8. , 2018, Salvador. Anais [...]. Porto Alegre: Sociedade Brasileira de Computação, 2018 . p. 195-200. ISSN 2237-5430.