A Coarse-Grained Reconfigurable Architecture for a PRET Machine
Precision Timed (PRET) Machines are architectures designed for use in embedded real-time and cyber-physical systems that provide predictable and repeatable timing properties. Among the characteristics that allow a PRET to achieve such timing properties is the interleaving of hardware threads, present in the majority of the PRET processors developed so far. One of the drawbacks of such thread interleaving is that, in applications that doesn't contain enough Thread-Level Parallelism (TLP), PRET processors suffer from high latencies as 4x or higher when compared to other architectures, and execute many No-Operations. To attack these problems, a Coarse-Grained Re-configurable Architecture is proposed. Results show that latency and throughput are improved without loosing the desired timing properties of PRET Machines.
I. Liu, J. Reineke, D. Broman, M. Zimmer, and E. A. Lee, “A pret microarchitecture implementation with repeatable timing and competitive performance,” in Computer Design (ICCD), 2012 IEEE 30th International Conference on. IEEE, 2012, pp. 87–93.
M. Zimmer, D. Broman, C. Shaver, and E. A. Lee, “Flexpret: A processor platform for mixed-criticality systems,” in Real-Time and Embedded Technology and Applications Symposium (RTAS), 2014 IEEE 20th. IEEE, 2014, pp. 101–110.
S. Andalam, P. Roop, and A.Girault, “Predictable multithreading of embedded applications using pret-c,” in 2010 8th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010). IEEE, 2010, pp. 159–168.
B. Lickly, I. Liu, S. Kim, H. D. Patel, S. A. Edwards, and E. A. Lee, “Predictable programming on a precision timed architecture,” in Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems. ACM, 2008, pp. 137–146.
B. De Sutter, P. Raghavan, and A. Lambrechts, “Coarse-grained reconfigurable array architectures,” in Handbook of signal processing systems. Springer, 2010, pp. 449–484.
J. L. Hennessy and D. A. Patterson, Computer architecture: a quantitative approach. Elsevier, 2011.
C. Ferdinand, R. Heckmann, M. Langenbach, F. Martin, M. Schmidt, H. Theiling, S. Thesing, and R. Wilhelm, “Reliable and precise wcet determination for a real-life processor,” in International Workshop on Embedded Software. Springer, 2001, pp. 469–485.
D. A. Patterson and D. R. Ditzel, “The case for the reduced instruction set computer,” ACM SIGARCH Computer Architecture News, vol. 8, no. 6, pp. 25–33, 1980.
J. Reineke, I. Liu, H. D. Patel, S. Kim, and E. A. Lee, “Pret dram controller: Bank privatization for predictability and temporal isolation,” in Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis. ACM, 2011, pp. 99–108.
M. B. Rutzig, A. C. S. Beck, and L. Carro, “A transparent and energy aware reconfigurable multiprocessor platform for simultaneous ilp and tlp exploitation,” in Proceedings of the Conference on Design, Automation and Test in Europe. EDA Consortium, 2013, pp. 1559– 1564.
M. Karunaratne, A. K. Mohite, T. Mitra, and L.-S. Peh, “Hycube: A cgra with reconfigurable single-cycle multi-hop interconnect,” in Design Automation Conference (DAC), 2017 54th ACM/EDAC/IEEE. IEEE, 2017, pp. 1–6.
J. Lopes, D. Sousa, and J. C. Ferreira, “Evaluation of cgra architecture for real-time processing of biological signals on wearable devices,” in ReConFigurable Computing and FPGAs (ReConFig), 2017 International Conference on. IEEE, 2017, pp. 1–7.
C. Kim, M. Chung, Y. Cho, M. Konijnenburg, S. Ryu, and J. Kim, “Ulp-srp: Ultra low power samsung reconfigurable processor for biomedical applications,” in Field-Programmable Technology (FPT), 2012 International Conference on. IEEE, 2012, pp. 329–334.
K. Patel and C. J. Bleakley, “Coarse grained reconfigurable array based architecture for low power real-time seizure detection,” Journal of Signal Processing Systems, vol. 82, no. 1, pp. 55–68, 2016.
L. Duch, S. Basu, R. Braojos, D. Atienza, G. Ansaloni, and L. Pozzi, “A multi-core reconfigurable architecture for ultra-low power bio-signal analysis,” in Biomedical Circuits and Systems Conference (BioCAS), 2016 IEEE. IEEE, 2016, pp. 416–419.