Evaluating dead-line predictors efficiency with drowsy technique
In recent years, the constant reduction on the transistor size allowed the cache memories to greatly growth in capacity. Nowadays, the cache memories occupy near to 50% of the processor's chip area; this increase was also driven by the memory wall and dark silicon issues. However, this capacity growth influences the energy consumption to maintain the data and operate over such big cache memories. This makes the energy consumed by the caches an important study area. There are many existing methods to save the energy consumed by these caches. In this paper, we evaluate the integration of existing dead cache line predictors and the drowsy cache technique in order to analyze the benefits in terms of energy consumption and execution time.
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