A manycore vision processor architecture for embedded applications
Real-Time Image Processing and Computer Vision systems are now in the mainstream of technologies enabling applications for Cyber-Physical Systems, Internet of Things, Augmented Reality, and Industry 4.0. These applications bring the need for Smart Camera for local real-time processing of images and videos. However, the massive amount of data to be processed within short deadlines cannot be handled by most commercial cameras. In this work, we show the design and implementation of a many-core vision processor architecture to be used in Smart Cameras. With massive parallelism exploration and application-specific characteristics, our architecture is composed of distributed Processing Elements and Memories connected through a Network-on-Chip. The architecture was implemented as an FPGA overlay, focusing on optimized hardware utilization. The parameterized architecture was characterized by its hardware occupation, maximum operating frequency, and processing frame rate. Different configurations ranging from one to four hundred Processing Elements were implemented and compared to several works from the literature. The results show that the proposed architecture successfully allies programmability and performance, being a suitable alternative for future Smart Cameras.
J. Yudi C. H. Llanos and M. Huebner "System-level design space identification for many-core vision processors" Microprocessors and Microsystems 2017.
J. A. Schmitz M. K. Gharzai S. Balkir M. W. Hoffman D. J. White and N. Schemm "A 1000 frames/s vision chip using scalable pixel-neighborhood-level parallel processing" IEEE Journal of Solid-State Circuits 2017.
J. Y. Mori C. H. Llanos and P. A. Berger "Kernel analysis for architecture design trade off in convolution-based image filtering" 2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI) 2012.
M. A. Kadi B. Janssen J. Yudi and M. Huebner "General-purpose computing with soft gpus on fpgas" ACM Trans. Reconfigurable Technol. Syst. 2018.
J. Hoozemans R. de Jong S. van der Vlugt J. V. Straten U. K. Elango and Z. Al-Ars "Frame-based programming stream-based processing for medical image processing applications" Journal of Signal Processing Systems 2019.
A. Ingole and V. Agarwal "Instruction set design for elementary set in tensilica xtensa" 2019 10th International Conference on Computing Communication and Networking Technologies (ICCCNT) 2019.
J. Joshi S. Bade P. Batra and R. Adyanthaya "Real time image processing system using packet based on chip communication" The National Conference on Communications 2007.
J. Joshi K. Karandikar S. Bade M. Bodke R. Adyanthaya and B. Ahirwal "Multi-core image processing system using network on chip interconnect" 2007 50th Midwest Symposium on Circuits and Systems pp. 1257-1260 2007.
V. Fresse A. Aubert and N. Bochard "A predictive noc architecture for vision systems dedicated to image analysis" EURASIP Journal on Embedded Systems 2007.
S. Saponara L. Fanucci and E. Petri "A multi-processor noc-based architecture for real-time image/video enhancement" Journal of Real-Time Image Processing 2013.
J. A. Ross D. A. Richie and S. J. Park "Implementing image processing algorithms for the epiphany many-core coprocessor with threaded mpi" 2015 IEEE High Performance Extreme Computing Conference 2015.
S. Lee and C. Yang "A real time object recognition and counting system for smart industrial camera sensor" IEEE Sensors Journal vol. 17 no. 8 pp. 2516-2523 2017.
K. M. Ali R. B. Atitallah S. Hanafi and J.-L. Dekeyser "A generic pixel distribution architecture for parallel video processing" 2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) 2014.
M. F. Aydogdu M. F. Demirci and C. Kasnakoglu "Pipelining harris corner detection with a tiny fpga for a mobile robot" 2013 IEEE International Conference on Robotics and Biomimetics (ROBIO) 2013.
K. Khalil O. Eldash A. Kumar and M. Bayoumi "A speed and energy focused framework for dynamic hardware reconfiguration" 2019 32nd IEEE International System-on-Chip Conference (SOCC) pp. 388-393 2019.
Vivado Design Suite User Guide - Synthesis Xilinx 2020.
W. Burger and M. Burge Digital Image Processing: An Algorithmic Introduction Using Java ser. Texts in Computer Science London:Springer 2016.
C. Harris and M. Stephens "A combined corner and edge detector" Proc. of Fourth Alvey Vision Conference pp. 147-151 1988.
P. R. Possa S. A. Mahmoudi N. Harb C. Valderrama and P. Manneback "A multi-resolution fpga-based architecture for real-time edge and corner detection" IEEE Transactions on Computers 2014.
A. Amaricai C. Gavriliu and O. Boncalo "An fpga sliding window-based architecture harris corner detector" 2014 24th International Conference on Field Programmable Logic and Applications (FPL) 2014.
E. R. Sousa A. Tanase F. Hannig and J. Teich "Accuracy and performance analysis of harris corner computation on tightly-coupled processor arrays" 2013 Conference on Design and Architectures for Signal and Image Processing 2013.
S. Liu C. Lyu Y. Liu W. Zhou X. Jiang P. Li et al. "Real-time implementation of harris corner detection system based on fpga" 2017 IEEE International Conference on Real-time Computing and Robotics (RCAR) 2017.
F. Hosseini A. Fijany and J.-G. Fontaine "Highly parallel implementation of harris corner detector on csx simd architecture" Euro-Par 2010 Parallel Processing Workshops 2011.
H. Chahuara and P. Rodríguez "Real-time corner detection on mobile platforms using cuda" 2018 IEEE XXV International Conference on Electronics Electrical Engineering and Computing (INTERCON) 2018.
L. Suriano F. Arrestier A. Rodríguez J. Heulot K. Desnos M. Pelcat et al. "Damhse: Programming heterogeneous mpsocs with hardware acceleration using dataflow-based design space exploration and automated rapid prototyping" Microprocessors and Microsystems 2019.
J. Rettkowski and D. Göhringer "Sdmpsoc: Software-defined mpsoc for fpgas" Journal of Signal Processing Systems 2019.