Mapping Computations in Heterogeneous Multicore Systems with Statistical Regression on Inputs
The use of hybrid Networks-on-Chip has increased in the scenario of communication in MP-SoCs, combining the advantages of different approaches. While a wired-wireless network can bring improvements in latency and power consumption, in some scenarios it presents a greater packet loss rate than in wired NoCs during communication. The purpose of this paper is to map the links that interconnect the wired and wireless routers so that we can optimize the network and achieve a trade-off between the average latency of the network and the number of delivered packets. To assess the mapping, three different topologies are tested, along with three different traffic patterns and three different injection rates. Experimental results show that for most cases it was possible to optimize the hybrid networks, achieving up to 80% of delivered packets, while reducing latencyby rates up to 5 times
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