Mapping Computations in Heterogeneous Multicore Systems with Statistical Regression on Inputs
Resumo
The use of hybrid Networks-on-Chip has increased in the scenario of communication in MP-SoCs, combining the advantages of different approaches. While a wired-wireless network can bring improvements in latency and power consumption, in some scenarios it presents a greater packet loss rate than in wired NoCs during communication. The purpose of this paper is to map the links that interconnect the wired and wireless routers so that we can optimize the network and achieve a trade-off between the average latency of the network and the number of delivered packets. To assess the mapping, three different topologies are tested, along with three different traffic patterns and three different injection rates. Experimental results show that for most cases it was possible to optimize the hybrid networks, achieving up to 80% of delivered packets, while reducing latencyby rates up to 5 times
Palavras-chave:
Wireless Network-on-Chip, Network-on-Chip, Hybrid Network, Mapping
Referências
A.-C. Orgerie M. D. d. Assuncao and L. Lefevre "A survey on techniques for improving the energy efficiency of large-scale distributed systems" ACM Comput. Surv. vol. 46 no. 4 pp. 47:1-47:31 2014.
G. Semeraro G. Magklis R. Balasubramonian D. H. Albonesi S. Dwarkadas and M. L. Scott "Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling" HPCA 2002.
M. Hahnel and H. Hartig "Heterogeneity by the numbers: A study of the odroid xu+e big. little platform" in HotPower Berkeley CA USA:USENIX Association pp. 3-3 2014.
P. Greenhalgh big. LITTLE processing with ARM cortex-A15 & cortex-A7 pp. 1-8 2011.
M. W. Azhar M. Pericas and P. Stenstrom "SaC: Exploiting execution-time slack to save energy in heterogeneous multicore systems" ICPP pp. 26:1-26:12 2019.
A. Jundt A. Cauble-Chantrenne A. Tiwari J. Peraza M. A. Laurenzano and L. Carrington "Compute bottlenecks on the new 64-bit arm" E2SC pp. 6:1-6:7 2015.
O. Khan and S. Kundu "A self-adaptive scheduler for asymmetric multi-cores" GLSVLSI pp. 397-400 2010.
M. Nejat M. Pericas and P. Stenstrom "QoS-driven coordinated management of resources to save energy in multi-core systems" IPDPS pp. 303-313 2019.
R. Nishtala P. M. Carpenter V. Petrucci and X. Martorell "Hipster: Hybrid task manager for latency-critical cloud workloads" HPCA pp. 409-420 2017.
V. Petrucci O. Loques D. Mosse R. Melhem N. A. Gazala and S. Gob-riel "Energy-efficient thread assignment optimization for heterogeneous multicore systems" ACM Trans. Embed. Comput. Syst. vol. 14 no. 1 pp. 15:1-15:26 2015.
J. K. V. Sreelatha S. Balachandran and R. Nasre "CHOAMP: cost based hardware optimization for asymmetric multicore processors" Trans. Multi-Scale Computing Systems vol. 4 no. 2 pp. 163-176 2018.
D. Shelepov J. C. Saez Alcaide S. Jeffery A. Fedorova N. Perez Z. F. Huang et al. "HASS: A scheduler for heterogeneous multicore systems" SIGOPS Oper. Syst. Rev. vol. 43 no. 2 pp. 66-75 2009.
R. Vallee-Rai P. Co E. Gagnon L. Hendren P. Lam and V. Sundaresan "Soot - a java bytecode optimization framework" in CASCON Indianapolis US:IBM Press 1999.
J. Shun G. E. Blelloch J. T. Fineman P. B. Gibbons A. Kyrola H. V. Simhadri et al. "Brief announcement: The problem based benchmark suite" SPAA pp. 68-70 2012.
U. A. Acar A. Chargueraud A. Guatto M. Rainey and F. Sieczkowski "Heartbeat scheduling: Provable efficiency for nested parallelism" PLDI pp. 769-782 2018.
A. Prokopec A. Rosa D. Leopoldseder G. Duboscq P. Tuma M. Stu-dener et al. "Renaissance: Benchmarking suite for parallel applications on the jvm" PLDI pp. 31-47 2019.
B. Jeff big. LITTLE technology moves towards fully heterogeneous global task scheduling 2013.
P. Nie and Z. Duan "Efficient and scalable scheduling for performance heterogeneous multicore systems" J. Parallel Distrib. Comput. vol. 72 no. 3 pp. 353-361 2012.
J. M. Kim S. K. Seo and S. W. Chung Looking into heterogeneity: when simple is faster 2014.
J. C. R. da Silva F. M. Q. Pereira M. Frank and A. Gamatie "A compiler-centric infra-structure for whole-board energy measurement on heterogeneous android systems" ReCoSoC pp. 1-8 2018.
F. David G. Thomas J. Lawall and G. Muller "Continuously measuring critical section pressure with the free-lunch profiler" SIGPLAN Not. vol. 49 no. 10 pp. 291-307 2014.
M. A. Cauchy "Methode generale pour la resolution des systemes d'Equations simultanees" Comptes Rendus Hebd. Seances Acad. Sci. vol. 25 no. 10 pp. 536-538 1847.
T. Bessa G. Gull P. Q. Ao M. Frank J. Nacif and F. M. Q. ao Pereira "JetsonLEAP: A framework to measure power on a heterogeneous system-on-a-chip device" Science of Computer Programming vol. 33 no. 1 pp. 1-37 2017.
F. Pedregosa G. Varoquaux A. Gramfort V. Michel B. Thirion O. Grisel et al. "Scikit-learn: Machine learning in Python" Journal of Machine Learning Research vol. 12 pp. 2825-2830 2011.
P. Butcher Seven Concurrency Models in Seven Weeks Raleigh NC US:Pragmatic Bookshelf 2014.
V. J. Reddi S. Kanev W. Kim S. Campanoni M. D. Smith G.-Y. Wei et al. "Voltage smoothing: Characterizing and mitigating voltage noise in production processors via software-guided thread scheduling" MICRO pp. 77-88 2010.
J. C. Ribeiro da Silva L. Leao V. Petrucci A. Gamatie and F. M. Quintao Pereira Scheduling in Heterogeneous Architectures via Multivariate Linear Regression on Function Inputs Sep. 2019.
Z. Wang and M. F. P. O'Boyle "Machine learning in compiler optimization" Proc. IEEE vol. 106 no. 11 pp. 1879-1901 2018.
A. H. Ashouri W. Killian J. Cavazos G. Palermo and C. Silvano "A survey on compiler autotuning using machine learning" Comput. Surv. vol. 51 no. 5 pp. 96:1-96:42 2018.
S. Mittal "A survey of techniques for architecting and managing asymmetric multicore processors" Comput. Surv. vol. 48 no. 3 pp. 45:1-45:38 2016.
H. Cai Q. Cao F. Sheng M. Zhang C. Qi J. Yao et al. "Mont-golfier: Latency-aware power management system for heterogeneous servers" IPCCC pp. 1-8 2016.
A. Garcia-Garcia J. C. Saez and M. Prieto "Contention-aware fair scheduling for asymmetric single-isa multicore systems" IEEE Trans. Computers vol. 67 no. 12 pp. 1703-1719 2018.
K. Van Craeynest A. Jaleel L. Eeckhout P. Narvaez and J. Emer "Scheduling heterogeneous multi-cores through performance impact estimation (PIE)" ISCA pp. 213-224 2012.
J. Krishna and R. Nasre "Optimizing graph algorithms in asymmsetric multicore processors" Trans. on CAD of Integrated Circuits and Systems vol. 37 no. 11 pp. 2673-2684 2018.
G. Semeraro G. Magklis R. Balasubramonian D. H. Albonesi S. Dwarkadas and M. L. Scott "Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling" HPCA 2002.
M. Hahnel and H. Hartig "Heterogeneity by the numbers: A study of the odroid xu+e big. little platform" in HotPower Berkeley CA USA:USENIX Association pp. 3-3 2014.
P. Greenhalgh big. LITTLE processing with ARM cortex-A15 & cortex-A7 pp. 1-8 2011.
M. W. Azhar M. Pericas and P. Stenstrom "SaC: Exploiting execution-time slack to save energy in heterogeneous multicore systems" ICPP pp. 26:1-26:12 2019.
A. Jundt A. Cauble-Chantrenne A. Tiwari J. Peraza M. A. Laurenzano and L. Carrington "Compute bottlenecks on the new 64-bit arm" E2SC pp. 6:1-6:7 2015.
O. Khan and S. Kundu "A self-adaptive scheduler for asymmetric multi-cores" GLSVLSI pp. 397-400 2010.
M. Nejat M. Pericas and P. Stenstrom "QoS-driven coordinated management of resources to save energy in multi-core systems" IPDPS pp. 303-313 2019.
R. Nishtala P. M. Carpenter V. Petrucci and X. Martorell "Hipster: Hybrid task manager for latency-critical cloud workloads" HPCA pp. 409-420 2017.
V. Petrucci O. Loques D. Mosse R. Melhem N. A. Gazala and S. Gob-riel "Energy-efficient thread assignment optimization for heterogeneous multicore systems" ACM Trans. Embed. Comput. Syst. vol. 14 no. 1 pp. 15:1-15:26 2015.
J. K. V. Sreelatha S. Balachandran and R. Nasre "CHOAMP: cost based hardware optimization for asymmetric multicore processors" Trans. Multi-Scale Computing Systems vol. 4 no. 2 pp. 163-176 2018.
D. Shelepov J. C. Saez Alcaide S. Jeffery A. Fedorova N. Perez Z. F. Huang et al. "HASS: A scheduler for heterogeneous multicore systems" SIGOPS Oper. Syst. Rev. vol. 43 no. 2 pp. 66-75 2009.
R. Vallee-Rai P. Co E. Gagnon L. Hendren P. Lam and V. Sundaresan "Soot - a java bytecode optimization framework" in CASCON Indianapolis US:IBM Press 1999.
J. Shun G. E. Blelloch J. T. Fineman P. B. Gibbons A. Kyrola H. V. Simhadri et al. "Brief announcement: The problem based benchmark suite" SPAA pp. 68-70 2012.
U. A. Acar A. Chargueraud A. Guatto M. Rainey and F. Sieczkowski "Heartbeat scheduling: Provable efficiency for nested parallelism" PLDI pp. 769-782 2018.
A. Prokopec A. Rosa D. Leopoldseder G. Duboscq P. Tuma M. Stu-dener et al. "Renaissance: Benchmarking suite for parallel applications on the jvm" PLDI pp. 31-47 2019.
B. Jeff big. LITTLE technology moves towards fully heterogeneous global task scheduling 2013.
P. Nie and Z. Duan "Efficient and scalable scheduling for performance heterogeneous multicore systems" J. Parallel Distrib. Comput. vol. 72 no. 3 pp. 353-361 2012.
J. M. Kim S. K. Seo and S. W. Chung Looking into heterogeneity: when simple is faster 2014.
J. C. R. da Silva F. M. Q. Pereira M. Frank and A. Gamatie "A compiler-centric infra-structure for whole-board energy measurement on heterogeneous android systems" ReCoSoC pp. 1-8 2018.
F. David G. Thomas J. Lawall and G. Muller "Continuously measuring critical section pressure with the free-lunch profiler" SIGPLAN Not. vol. 49 no. 10 pp. 291-307 2014.
M. A. Cauchy "Methode generale pour la resolution des systemes d'Equations simultanees" Comptes Rendus Hebd. Seances Acad. Sci. vol. 25 no. 10 pp. 536-538 1847.
T. Bessa G. Gull P. Q. Ao M. Frank J. Nacif and F. M. Q. ao Pereira "JetsonLEAP: A framework to measure power on a heterogeneous system-on-a-chip device" Science of Computer Programming vol. 33 no. 1 pp. 1-37 2017.
F. Pedregosa G. Varoquaux A. Gramfort V. Michel B. Thirion O. Grisel et al. "Scikit-learn: Machine learning in Python" Journal of Machine Learning Research vol. 12 pp. 2825-2830 2011.
P. Butcher Seven Concurrency Models in Seven Weeks Raleigh NC US:Pragmatic Bookshelf 2014.
V. J. Reddi S. Kanev W. Kim S. Campanoni M. D. Smith G.-Y. Wei et al. "Voltage smoothing: Characterizing and mitigating voltage noise in production processors via software-guided thread scheduling" MICRO pp. 77-88 2010.
J. C. Ribeiro da Silva L. Leao V. Petrucci A. Gamatie and F. M. Quintao Pereira Scheduling in Heterogeneous Architectures via Multivariate Linear Regression on Function Inputs Sep. 2019.
Z. Wang and M. F. P. O'Boyle "Machine learning in compiler optimization" Proc. IEEE vol. 106 no. 11 pp. 1879-1901 2018.
A. H. Ashouri W. Killian J. Cavazos G. Palermo and C. Silvano "A survey on compiler autotuning using machine learning" Comput. Surv. vol. 51 no. 5 pp. 96:1-96:42 2018.
S. Mittal "A survey of techniques for architecting and managing asymmetric multicore processors" Comput. Surv. vol. 48 no. 3 pp. 45:1-45:38 2016.
H. Cai Q. Cao F. Sheng M. Zhang C. Qi J. Yao et al. "Mont-golfier: Latency-aware power management system for heterogeneous servers" IPCCC pp. 1-8 2016.
A. Garcia-Garcia J. C. Saez and M. Prieto "Contention-aware fair scheduling for asymmetric single-isa multicore systems" IEEE Trans. Computers vol. 67 no. 12 pp. 1703-1719 2018.
K. Van Craeynest A. Jaleel L. Eeckhout P. Narvaez and J. Emer "Scheduling heterogeneous multi-cores through performance impact estimation (PIE)" ISCA pp. 213-224 2012.
J. Krishna and R. Nasre "Optimizing graph algorithms in asymmsetric multicore processors" Trans. on CAD of Integrated Circuits and Systems vol. 37 no. 11 pp. 2673-2684 2018.
Publicado
23/11/2020
Como Citar
DA SILVA, Junio; LEÃO, Lorena; PETRUCCI, Vinicius; GAMATIÉ, Abdoulaye; PEREIRA, Fernando.
Mapping Computations in Heterogeneous Multicore Systems with Statistical Regression on Inputs. In: SIMPÓSIO BRASILEIRO DE ENGENHARIA DE SISTEMAS COMPUTACIONAIS (SBESC), 10. , 2020, Evento Online.
Anais [...].
Porto Alegre: Sociedade Brasileira de Computação,
2020
.
p. 159-166.
ISSN 2237-5430.
