On the Selection of Relevant Hardware Events for Explaining Execution Time Behaviour

• Tadeu Nogueira C. Andrade UFBA
• George Lima UFBA
• Veronica Maria Cadena Lima UFBA
• Yasmina Abdeddaïm Université Gustave Eiffel
• Liliana Cucu Grosjean INRIA

Resumo

Estimating safe upper bounds on task execution times is required in the design of predictable real-time systems. When multi-core, instruction pipeline, branch prediction, or cache memory are in place, due to the considerable complexity static timing analysis faces, measurement-based timing analysis (MBTA) is a more tractable option. MBTA estimates upper bounds on execution times using data measured under the execution of representative scenarios. In this context, it is paramount understanding not only how the task execution time is affected during its execution but also what kind of interference the task is sensitive to. Events such as cache misses or pipeline stalls, for example, may lead to large variability in task execution times. Based on the fact that current platforms offer Performance Monitoring Units (PMUs) capable of counting hardware-level event occurrences, in this paper, we focus on the problem of selecting the events that have the most impact on task execution with the goal of enriching the collected information to better support MBTA. Unfortunately, PMU usually have a limited number of monitoring registers, making them unable to monitor all events at once. Our approach describes how to carry out the events selection even under this limitation. Results from our experiments, considering 15 different programs running on a Raspberry Pi, indicate that five selected events can explain the execution behavior of the programs with reasonable accuracy.

Palavras-chave: Upper bound, Pipelines, Real-time systems, Phasor measurement units, Hardware, Timing, Complexity theory, real-time systems, hardware events, measurement-based timing analysis, multi-core architectures